GP2021 datasheet(29/62 Pages) MITEL

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GP2021

CHx_ACCUM_RESET

(Write Address)

Bits 15 to 0: Not used.

These are write–only locations provided to allow

resetting of the status bits ACCUM_STATUS_A,

ACCUM_STATUS_B, and ACCUM_STATUS_C associated

with a given channel or all channels. When these locations are

written to, the data is irrelevant.

CHx_CARRIER_CYCLE_COUNTER,

MULTI_CARRIER_CYCLE_COUNTER,

ALL _CARRIER_CYCLE_COUNTER

(Write Address)

A write to these registers only has effect when in test

mode (bit 3 of TEST_CONTROL set High). The value on the

bus

loaded

into

the

lower

bits

the

CHx_CARRIER_CYCLE_COUNTER along with zeros into

the upper 4 bits.

CHx_CARRIER_CYCLE_HIGH,

CHx_CARRIER_CYCLE_LOW

(Read Address)

_HIGH bits 15 to 4 : not used – LOW when read.

_HIGH bits 3 to 0: Carrier Cycle Count bits 19 to 16.

_LOW bits 15 to 0: Carrier Cycle Count bits 15 to 0.

The Correlator tracking channel hardware allows for

measurement of integrated carrier phase through the

CHx_CARRIER_CYCLE_HIGH and _LOW and the

CHx_CARRIER_DCO_PHASE registers, which are part of

the Measurement Data sampled at every TIC. The

CHx_CARRIER_CYCLE_HIGH and _LOW registers contain

the 20 bit number of positive going zero crossings of the

Carrier DCO (4 bits are in _HIGH and 16 in _LOW). The cycle

fraction can be read from the CHx_Carrier_DCO_Phase

In the CHx_CARRIER_CYCLE counter, a TIC

generates two consecutive actions. First it latches the 4 more

significant

bits

the

cycle

counter

into

CHx_CARRIER_CYCLE_HIGH and the 16 less significant

bits into CHx_CARRIER_CYCLE_LOW. Then it resets the

cycle counter.

After each TIC, every time the Carrier DCO accumulator

generates an overflow as a result of a carrier cycle being

completed, the cycle counter increments by one.

In Real_Input mode the nominal CARRIER DCO

frequency with no Doppler and no oscillator drift

compensation is 1·405396825 MHz, so in 100 ms, there will

be about 140540 cycles.

In almost all applications the number of Carrier DCO

cycles does not vary much from one TIC interval to another so

it is possible to predict the Most Significant Bits of the value,

and then only read the CHx_CARRIER_CYCLE_LOW

CHx_CARRIER_CYCLE_HIGH and _LOW contents are

not protected by an overwrite protection mechanism and so

must be read before the next TIC.

For further information on the Carrier Cycle Counter refer to

Detailed Operation of GP2021.*

* Refer to page 9.

CHx_CARRIER_DCO_INCR_HIGH,

X_DCO_INCR_HIGH,

MULTI_CARRIER_DCO_INCR_HIGH,

ALL_CARRIER_DCO_INCR_HIGH,

CHx_CARRIER_DCO_INCR_LOW,

MULTI_CARRIER_DCO_INCR_LOW,

ALL_CARRIER_DCO_INCR_LOW

(Write Address)

_INCR_HIGH bits 15 to 10: Not used in this operation.

_INCR_HIGH bits 9 to 0 : More significant bits (25 to 16) of the

Carrier DCO phase increment when used before a write to

_CARRIER_DCO_INCR_LOW.

_INCR_LOW bits 15 to 0 : Less significant bits (15 to 0) of the

Carrier DCO phase increment.

The

contents

registers

_INCR_HIGH

and_INCR_LOW are combined to form the 26 bits of the

CHx_CARRIER_DCO_INCR register, the carrier DCO phase

increment number. In order to write successfully, the top 10

bits must be written first, to any of the _HIGH addresses. They

will be stored in a buffer and only be transferred into the

increment register of the DCO together with the _LOW word.

A 26 bit increment number is adequate for a 27 bit accumulator

DCO, as the increment to the MSB is always zero.

The LSB of the INCR register represents a step given by:

Min Step Frequency

= (40MHz/7)/2 27

(in Real_Input mode)

= 42.57475mHz

Min Step Frequency

= (35MHz/6)/2 27

(in Complex_Input mode)

= 43.46172mHz

The output Frequency

= CHx_CARRIER_DCO_INCR

* Min Step Frequency.

With a GP2015/GP2010 style front end, the nominal

value of the IF is 1.405396826 MHz before allowing for

Doppler shift or crystal error. Writing 01F7B1B9H into the

CHx_CARRIER_DCO_INCR register will generate a local

oscillator frequency of 1.405396845 MHz.

CHx_CARRIER_DCO_PHASE

(Read Address)

Bits 15 to 10: Not used – Low when read.

Bits 9 to 0: More significant bits (26 to 17) of

CHx_CARRIER_DCO_PHASE as sampled at the last TIC.

The weight of the least significant bit is 2

π / 1024 radians of

a Carrier DCO cycle. These bits form an unsigned integer valid

from 0 to 1023. CHx_CARRIER_DCO_PHASE provides

ACCUM_STATUS_C bits are sampled and latched on

the active edge of every ACCUM_INT signal, or they can be

sampled and latched on request by performing a write

operation to STATUS (as with ACCUM_STATUS_A).

CHx_EARLY_LATEB status bit indicates the code type

for the Accumulated Data on the Tracking arm of channel CHx

when that channel is in Dithering mode. A High indicates an

EARLY code and a Low indicates a LATE code. Each

individual bit is determined on the DUMP that sets

CHx_NEW_ACCUM_DATA to High for that channel. In other

modes the bit is of no use.

Note that the channel specific bits of this register will not

show their new value until after an active edge of ACCUM_INT

or a write to the STATUS register. Disabling a channel will

however, clear the bit immediately.

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