GP2021 datasheet(46/62 Pages) MITEL

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GP2021

Notes :

Although MULTI_FN_IO is capable of being used as a Discrete input, this is not advised since if this pin is

driven High at power up, Digital Test Mode will be selected and correct operation will not ensue.

Output has power level 1 when OPS_DRIVE_SEL is Low in the SYSTEM_SETUP Register.

Output has power level 2 when OPS_DRIVE_SEL is High in the SYSTEM_SETUP Register.

Input has TTL thresholds in ARM System mode, but has Schmitt Trigger (type ST2) thresholds in Standard

Interface mode.

Output has power level 3 when OPS_DRIVE_SEL is Low in the SYSTEM_SETUP Register.

Output has power level 6 when OPS_DRIVE_SEL is High in the SYSTEM_SETUP Register.

Input has Schmitt Trigger type ST2 thresholds when IPS_3V_MODE is Low in the SYSTEM_SETUP

Usually connected to NFIQ of the ARM60 Processor.

Usually connected to NIRQ of the ARM60 Processor.

Characterisation data for this pin is with C L = 10pF.

Characterisation data for this pin is with C L = 20pF.

10. Characterisation data for this pin is with C L = 30pF

11. Characterisation data for this pin is with C L = 50pF.

12. Characterisation data for this pin is with C L = 55pF.

13. Setup and Hold times for the GPS data applied on pins SIGN0, MAG0, SIGN1 and MAG1 are with respect to

the rising edge of SAMPCLK. Setup time = 15ns, Hold time = –1ns (i.e. data should not change during the

period between 15ns and1ns before the rising edge of SAMPCLK; where SAMPCLK is assumed to be un

loaded. The SAMPCLK signal will tend to be further delayed by about 0.1ns / pF of load capacitance).

VDD

100k

CLK_T

CLK_I

100k

0.1 TO 1nF

600mV

SINE

WAVE

180k

0.1 TO 1nF

CLK_T

CLK_I

GP2010

DIFFERENTIAL

OUTPUT

OPCLK+

CLK_T

OPCLK–

CLK_I

VSS

SINGLE ENDED CMOS

DIFFERENTIAL

SINGLE 600mV SINEWAVE

100k

Fig 24 : Clock interconnect options

GP2021 数据表(PDF) 46 Page - Mitel Networks Corporation

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