80C32EBAA datasheet(43/62 Pages) PHILIPS

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Philips Semiconductors

Product specification

80C52/80C54/80C58

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier. The pins can be configured for use as an on-chip

oscillator.

To drive the device from an external clock source, XTAL1 should be

driven while XTAL2 is left unconnected. There are no requirements

on the duty cycle of the external clock signal, because the input to

the internal clock circuitry is through a divide-by-two flip-flop.

However, minimum and maximum high and low times specified in

the data sheet must be observed.

Reset

A reset is accomplished by holding the RST pin high for at least two

machine cycles (24 oscillator periods), while the oscillator is running.

To insure a good power-on reset, the RST pin must be high long

enough to allow the oscillator time to start up (normally a few

milliseconds) plus two machine cycles. At power-on, the voltage on

VCC and RST must come up at the same time for a proper start-up.

Ports 1, 2, and 3 will asynchronously be driven to their reset

condition when a voltage above VIH1 (min.) is applied to RESET.

Idle Mode

In the idle mode (see Table 6), the CPU puts itself to sleep while all

of the on-chip peripherals stay active. The instruction to invoke the

idle mode is the last instruction executed in the normal operating

mode before the idle mode is activated. The CPU contents, the

on-chip RAM, and all of the special function registers remain intact

during this mode. The idle mode can be terminated either by any

enabled interrupt (at which time the process is picked up at the

interrupt service routine and continued), or by a hardware reset

which starts the processor in the same manner as a power-on reset.

Power-Down Mode

To save even more power, a Power Down mode (see Table 6) can

be invoked by software. In this mode, the oscillator is stopped and

the instruction that invoked Power Down is the last instruction

executed. The on-chip RAM and Special Function Registers retain

their values until the Power Down mode is terminated.

On the 80C52/54/58 either a hardware reset or external interrupt

can be used to exit from Power Down. Reset redefines all the SFRs

but does not change the on-chip RAM. An external interrupt allows

both the SFRs and the on-chip RAM to retain their values.

To properly terminate Power Down the reset or external interrupt

should not be executed before VCC is restored to its normal

operating level and must be held active long enough for the

oscillator to restart and stabilize (normally less than 10ms).

With an external interrupt, INT0 and INT1 must be enabled and

configured as level-sensitive. Holding the pin low restarts the

oscillator but bringing the pin back high completes the exit. Once the

interrupt is serviced, the next instruction to be executed after RETI

will be the one following the instruction that put the device into

Power Down.

Design Consideration

• When the idle mode is terminated by a hardware reset, the device

normally resumes program execution, from where it left off, up to

two machine cycles before the internal rest algorithm takes

control. On-chip hardware inhibits access to internal RAM in this

event, but access to the port pins is not inhibited. To eliminate the

possibility of an unexpected write when Idle is terminated by reset,

the instruction following the one that invokes Idle should not be

one that writes to a port pin or to external memory.

ONCE

™ Mode

The ONCE (“On-Circuit Emulation”) Mode facilitates testing and

debugging of systems using the 80C52/54/58 without removing the

device from the circuit. The ONCE Mode is invoked by:

1. Pull ALE low while the device is in reset and PSEN is high;

2. Hold ALE low as RST is deactivated.

While the device is in ONCE Mode, the Port 0 pins go into a float

state, and the other port pins and ALE and PSEN are weakly pulled

high. The oscillator circuit remains active. While the 80C52/54/58 is

in this mode, an emulator or test CPU can be used to drive the

circuit. Normal operation is restored when a normal reset is applied.

Programmable Clock-Out

The 80C52/54/58 has a new feature. A 50% duty cycle clock can be

programmed to come out on P1.0. This pin, besides being a regular

I/O pin, has two alternate functions. It can be programmed:

1. to input the external clock for Timer/Counter 2, or

2. to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a

16MHz operating frequency.

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in

T2CON) must be cleared and bit T2OE in T2MOD must be set. Bit

TR2 (T2CON.2) also must be set to start the timer.

The Clock-Out frequency depends on the oscillator frequency and

the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)

as shown in this equation:

Oscillator Frequency

(65536

* RCAP2H, RCAP2L)

In the Clock-Out mode Timer 2 roll-overs will not generate an

interrupt. This is similar to when it is used as a baud-rate generator.

It is possible to use Timer 2 as a baud-rate generator and a clock

generator simultaneously. Note, however, that the baud-rate and the

Clock-Out frequency will be the same.

Table 6. External Pin Status During Idle and Power-Down Mode

MODE

PROGRAM

MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power-down

Internal

Data

Power-down

External

Float

Data

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