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80C32EBAA 数据表(PDF) 51 Page - NXP Semiconductors |
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80C32EBAA 数据表(HTML) 51 Page - NXP Semiconductors |
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51 / 62 page  Philips Semiconductors Product specification 80C52/80C54/80C58 CMOS single-chip 8-bit microcontrollers 1996 Aug 16 21 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 24MHz CLOCK VARIABLE CLOCK4 33MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX MIN MAX UNIT 1/tCLCL 13 Oscillator frequency Speed versions : I (24MHz) : N (33MHz) 3.5 24 3.5 33 3.5 33 MHz tLHLL 13 ALE pulse width 43 2tCLCL–40 21 ns tAVLL 13 Address valid to ALE low 17 tCLCL–25 5 ns tLLAX 13 Address hold after ALE low 17 tCLCL–25 ns tLLIV 13 ALE low to valid instruction in 102 4tCLCL–65 55 ns tLLPL 13 ALE low to PSEN low 17 tCLCL–25 5 ns tPLPH 13 PSEN pulse width 80 3tCLCL–45 45 ns tPLIV 13 PSEN low to valid instruction in 65 3tCLCL–60 30 ns tPXIX 13 Input instruction hold after PSEN 0 0 0 ns tPXIZ 13 Input instruction float after PSEN 17 tCLCL–25 5 ns tAVIV 13 Address to valid instruction in 128 5tCLCL–80 70 ns tPLAZ 13 PSEN low to address float 10 10 10 ns Data Memory tRLRH 14, 15 RD pulse width 150 6tCLCL–100 82 ns tWLWH 14, 15 WR pulse width 150 6tCLCL–100 82 ns tRLDV 14, 15 RD low to valid data in 118 5tCLCL–90 60 ns tRHDX 14, 15 Data hold after RD 0 0 0 ns tRHDZ 14, 15 Data float after RD 55 2tCLCL–28 32 ns tLLDV 14, 15 ALE low to valid data in 183 8tCLCL–150 90 ns tAVDV 14, 15 Address to valid data in 210 9tCLCL–165 105 ns tLLWL 14, 15 ALE low to RD or WR low 75 175 3tCLCL–50 3tCLCL+50 40 140 ns tAVWL 14, 15 Address valid to WR low or RD low 92 4tCLCL–75 45 ns tQVWX 14, 15 Data valid to WR transition 12 tCLCL–30 0 ns tWHQX 14, 15 Data hold after WR 17 tCLCL–25 5 ns tQVWH 15 Data valid to WR high 162 7tCLCL–130 80 ns tRLAZ 14, 15 RD low to address float 0 0 0 ns tWHLH 14, 15 RD or WR high to ALE high 17 67 tCLCL–25 tCLCL+25 5 55 ns External Clock tCHCX 17 High time 17 17 tCLCL–tCLCX ns tCLCX 17 Low time 17 17 tCLCL–tCHCX ns tCLCH 17 Rise time 5 5 ns tCHCL 17 Fall time 5 5 ns Shift Register tXLXL 16 Serial port clock cycle time 505 12tCLCL 360 ns tQVXH 16 Output data setup to clock rising edge 283 10tCLCL–133 167 ns tXHQX 16 Output data hold after clock rising edge 3 2tCLCL–80 ns tXHDX 16 Input data hold after clock rising edge 0 0 0 ns tXHDV 16 Clock rising edge to input data valid 283 10tCLCL–133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 80C52/54/58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz “AC Electrial Characteristics”, page 20. |
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