 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
80C32EBAA 数据表(PDF) 15 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
80C32EBAA 数据表(HTML) 15 Page - NXP Semiconductors |
|
|
15 / 62 page  Philips Semiconductors Product specification 80C32/87C52 CMOS single-chip 8-bit microcontrollers 1996 Aug 16 15 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (87C52)1, 2, 3 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 5 Oscillator frequency Speed versions : E 3.5 16 MHz tLHLL 5 ALE pulse width 85 2tCLCL–40 ns tAVLL 5 Address valid to ALE low 22 tCLCL–40 ns tLLAX 5 Address hold after ALE low 32 tCLCL–30 ns tLLIV 5 ALE low to valid instruction in 150 4tCLCL–100 ns tLLPL 5 ALE low to PSEN low 32 tCLCL–30 ns tPLPH 5 PSEN pulse width 142 3tCLCL–45 ns tPLIV 5 PSEN low to valid instruction in 82 3tCLCL–105 ns tPXIX 5 Input instruction hold after PSEN 0 0 ns tPXIZ 5 Input instruction float after PSEN 37 tCLCL–25 ns tAVIV 5 Address to valid instruction in 207 5tCLCL–105 ns tPLAZ 5 PSEN low to address float 10 10 ns Data Memory tRLRH 6, 7 RD pulse width 275 6tCLCL–100 ns tWLWH 6, 7 WR pulse width 275 6tCLCL–100 ns tRLDV 6, 7 RD low to valid data in 147 5tCLCL–165 ns tRHDX 6, 7 Data hold after RD 0 0 ns tRHDZ 6, 7 Data float after RD 65 2tCLCL–60 ns tLLDV 6, 7 ALE low to valid data in 350 8tCLCL–150 ns tAVDV 6, 7 Address to valid data in 397 9tCLCL–165 ns tLLWL 6, 7 ALE low to RD or WR low 137 239 3tCLCL–50 3tCLCL+50 ns tAVWL 6, 7 Address valid to WR low or RD low 122 4tCLCL–130 ns tQVWX 6, 7 Data valid to WR transition 13 tCLCL–50 ns tWHQX 6, 7 Data hold after WR 13 tCLCL–50 ns tQVWH 7 Data valid to WR high 287 7tCLCL–150 ns tRLAZ 6, 7 RD low to address float 0 0 ns tWHLH 6, 7 RD or WR high to ALE high 23 103 tCLCL–40 tCLCL+40 ns External Clock tCHCX 9 High time 20 20 tCLCL–tCLCX ns tCLCX 9 Low time 20 20 tCLCL–tCHCX ns tCLCH 9 Rise time 20 20 ns tCHCL 9 Fall time 20 20 ns Shift Register tXLXL 8 Serial port clock cycle time 750 12tCLCL ns tQVXH 8 Output data setup to clock rising edge 492 10tCLCL–133 ns tXHQX 8 Output data hold after clock rising edge 8 2tCLCL–117 ns tXHDX 8 Input data hold after clock rising edge 0 0 ns tXHDV 8 Clock rising edge to input data valid 492 10tCLCL–133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 80C32/52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interface. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
