80C32EBAA datasheet(14/62 Pages) PHILIPS

14 / 62 page

Philips Semiconductors

Product specification

80C32/87C52

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

DC ELECTRICAL CHARACTERISTICS

Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (87C52)

Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (80C32)

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP1

MAX

UNIT

VIL

Input low voltage, except EA7

–0.5

0.2VCC–0.1

VIL1

Input low voltage to EA7

0.2VCC–0.3

VIH

Input high voltage, except XTAL1, RST7

0.2VCC+0.9

VCC+0.5

VIH1

Input high voltage, XTAL1, RST7

0.7VCC

VCC+0.5

VOL

Output low voltage, ports 1, 2, 39

IOL = 1.6mA2

0.45

VOL1

Output low voltage, port 0, ALE, PSEN9

IOL = 3.2mA2

0.45

VOH

Output high voltage, ports 1, 2, 3, ALE, PSEN3

IOH = –60µA,

IOH = –25µA

IOH = –10µA

2.4

0.75VCC

0.9VCC

VOH1

Output high voltage (port 0 in external bus mode)

IOH = –800µA,

IOH = –300µA

IOH = –80µA

2.4

0.75VCC

0.9VCC

IIL

Logical 0 input current, ports 1, 2, 37

VIN = 0.45V

–50

µA

ITL

Logical 1-to-0 transition current, ports 1, 2, 37

See note 4

–650

µA

ILI

Input leakage current, port 0

VIN = VIL or VIH

±10

µA

ICC

Power supply current:7

Active mode @ 16MHz5

Idle mode @ 16MHz

Power-down mode

Tamb = 0 to 70°C

Tamb = –40 to +85°C

See note 6

11.5

1.3

µA

RRST

Internal reset pull-down resistor

300

Ω

CIO

Pin capacitance10

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the

address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when VIN is approximately 2V.

5. ICCMAX at other frequencies is given by: Active mode: ICCMAX = 1.5 × FREQ + 8.0: Idle mode: ICCMAX = 0.14 × FREQ +2.31,

where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 12.

6. See Figures 13 through 16 for ICC test conditions.

7. These values apply only to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, see table on previous page.

8. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

9. Under steady state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin:

15mA (*NOTE: This is 85

°C specification.)

Maximum IOL per 8-bit port:

26mA

Maximum total IOL for all outputs:

67mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

test conditions.

10. This limit is for plastic packages. For ceramic packages, the maximum limit is 20pF.

80C32EBAA 数据表(PDF) 14 Page - NXP Semiconductors

80C32EBAA 数据表(HTML) 14 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表下载