80C32EBAA datasheet(46/62 Pages) PHILIPS

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Philips Semiconductors

Product specification

80C52/80C54/80C58

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

SM0

SM1

SM2

REN

TB8

RB8

SCON

(98H)

COMPARATOR

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

IN UART MODE 2 OR MODE 3 AND SM2 = 1:

INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”

– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES

– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

SU00045

Figure 9. UART Multiprocessor Communication, Automatic Address Recognition

Interrupt Priority Structure

The 80C52/54/58 has a 6-source four-level interrupt structure. There

are 3 SFRs associated with the interrupts on the 80C52/54/58. They

are the IE and IP. (See Figures 10 and 11.) In addition, there is the

IPH (Interrupt Priority High) register that makes the four-level

interrupt structure possible. The IPH is located at SFR address B7H.

The structure of the IPH register and a description of its bits is

shown below:

IPH (Interrupt Priority High) (B7H)

–

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

IPH.0

PX0H External interrupt 0 priority high

IPH.1

PT0H Timer 0 interrupt priority high

IPH.2

PX1H External interrupt 1 priority high

IPH.3

PT1H Timer 1 interrupt priority high

IPH.4

PSH

Serial Port interrupt high

IPH.5

PT2H Timer 2 interrupt priority high

IPH.6

—

Not implemented

IPH.7

—

Not implemented

The function of the IPH SFR is simple and when combined with the

IP SFR determines the priority of each interrupt. The priority of each

interrupt is determined as shown in the following table:

PRIORITY BITS

INTERRUPT PRIORITY LEVEL

IPH.x

IP.x

INTERRUPT PRIORITY LEVEL

Level 0 (lowest priority)

Level 1

Level 2

Level 3 (highest priority)

The priority scheme for servicing the interrupts is the same as that

for the 80C51, except there are four interrupt levels on the

80C52/54/58 rather than two as on the 80C51. An interrupt will be

serviced as long as an interrupt of equal or higher priority is not

already being serviced. If an interrupt of equal or higher level priority

is being serviced, the new interrupt will wait until it is finished before

being serviced. If a lower priority level interrupt is being serviced, it

will be stopped and the new interrupt serviced. When the new

interrupt is finished, the lower priority level interrupt that was

stopped will be completed.

Table 7.

Interrupt Table

SOURCE

POLLING PRIORITY

REQUEST BITS

HARDWARE CLEAR?

VECTOR ADDRESS

IE0

N (L)1

Y (T)2

03H

TP0

0BH

IE1

N (L)

Y (T)

13H

TF1

1BH

R1, TI

23H

TF2, EXF2

2BH

PCA

CF, CCFn

n = 0–4

33H

NOTES:

1. L = Level activated

2. T = Transition activated

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