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80C32EBAA 数据表(PDF) 50 Page - NXP Semiconductors |
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80C32EBAA 数据表(HTML) 50 Page - NXP Semiconductors |
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50 / 62 page  Philips Semiconductors Product specification 80C52/80C54/80C58 CMOS single-chip 8-bit microcontrollers 1996 Aug 16 20 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 13 Oscillator frequency Speed versions : E 3.5 16 MHz tLHLL 13 ALE pulse width 85 2tCLCL–40 ns tAVLL 13 Address valid to ALE low 22 tCLCL–40 ns tLLAX 13 Address hold after ALE low 32 tCLCL–30 ns tLLIV 13 ALE low to valid instruction in 150 4tCLCL–100 ns tLLPL 13 ALE low to PSEN low 32 tCLCL–30 ns tPLPH 13 PSEN pulse width 142 3tCLCL–45 ns tPLIV 13 PSEN low to valid instruction in4 82 3tCLCL–105 ns tPXIX 13 Input instruction hold after PSEN 0 0 ns tPXIZ 13 Input instruction float after PSEN 37 tCLCL–25 ns tAVIV 13 Address to valid instruction in4 207 5tCLCL–105 ns tPLAZ 13 PSEN low to address float 10 10 ns Data Memory tRLRH 14, 15 RD pulse width 275 6tCLCL–100 ns tWLWH 14, 15 WR pulse width 275 6tCLCL–100 ns tRLDV 14, 15 RD low to valid data in 147 5tCLCL–165 ns tRHDX 14, 15 Data hold after RD 0 0 ns tRHDZ 14, 15 Data float after RD 65 2tCLCL–60 ns tLLDV 14, 15 ALE low to valid data in 350 8tCLCL–150 ns tAVDV 14, 15 Address to valid data in 397 9tCLCL–165 ns tLLWL 14, 15 ALE low to RD or WR low 137 239 3tCLCL–50 3tCLCL+50 ns tAVWL 14, 15 Address valid to WR low or RD low 122 4tCLCL–130 ns tQVWX 14, 15 Data valid to WR transition 13 tCLCL–50 ns tWHQX 14, 15 Data hold after WR 13 tCLCL–50 ns tQVWH 15 Data valid to WR high 287 7tCLCL–150 ns tRLAZ 14, 15 RD low to address float 0 0 ns tWHLH 14, 15 RD or WR high to ALE high 23 103 tCLCL–40 tCLCL+40 ns External Clock tCHCX 17 High time 20 20 tCLCL–tCLCX ns tCLCX 17 Low time 20 20 tCLCL–tCHCX ns tCLCH 17 Rise time 20 20 ns tCHCL 17 Fall time 20 20 ns Shift Register tXLXL 16 Serial port clock cycle time 750 12tCLCL ns tQVXH 16 Output data setup to clock rising edge 492 10tCLCL–133 ns tXHQX 16 Output data hold after clock rising edge 8 2tCLCL–117 ns tXHDX 16 Input data hold after clock rising edge 0 0 ns tXHDV 16 Clock rising edge to input data valid 492 10tCLCL–133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 80C52/54/58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interfacing. |
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