80C32EBAA datasheet(32/62 Pages) PHILIPS

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Philips Semiconductors

Product specification

80C52/80C54/80C58

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

853–1470 17196

DESCRIPTION

The 80C52/80C54/80C58 Single-Chip 8-Bit Microcontroller is

manufactured in an advanced CMOS process and is a derivative of

the 80C51 microcontroller family. The 80C52/80C54/80C58 has the

same instruction set as the 80C51.

This device provides architectural enhancements that make it

applicable in a variety of applications for general control systems.

The 80C52 contains 8k

× 8 ROM memory, the 80C54 contains

16k

× 8 ROM memory, and 80C58 contains 32k × 8 ROM memory, a

volatile 256

× 8 read/write data memory, four 8-bit I/O ports, three

16-bit timer/event counters, a multi-source, four-priority-level, nested

interrupt structure, an enhanced UART and on-chip oscillator and

timing circuits. For systems that require extra capability, the

80C52/54/58 can be expanded using standard TTL compatible

memories and logic.

Its added features make it an even more powerful microcontroller for

applications that require pulse width modulation, high-speed I/O and

up/down counting capabilities such as motor control. It also has a

more versatile serial channel that facilitates multiprocessor

communications.

See 87C52/80C32 and 87C54/87C58 data sheets for EPROM and

ROMless devices.

FEATURES

• 80C51 central processing unit

• Full static operation

• 8k × 8 ROM: 80C52;

16k

× 8 ROM: 80C54;

32k

× 8 ROM: 80C58;

all capable of addressing external memory to 64k bytes

– Two level program security system

– 64 byte encryption array

• 256 × 8 RAM, expandable externally to 64k bytes

• Speed range up to 33MHz

• Operating voltage 5V ±10%

• Three 16-bit timer/counters

– T2 is an up/down counter

• 6 interrupt sources

• 4 level priority

• Four 8-bit I/O ports

• Full-duplex enhanced UART

– Framing error detection

– Automatic address recognition

• Power control modes

– Idle mode

– Power-down mode

• Once (On Circuit Emulation) Mode

• Five package styles

• Programmable clock out

• Low EMI (Inhibit ALE)

• Second DPTR register

• Asynchronous port reset

PIN CONFIGURATIONS

T2/P1.0

T2EX/P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

RST

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

P1.7

WR/P3.6

RD/P3.7

XTAL2

XTAL1

VSS

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

VCC

DUAL

IN-LINE

PACKAGE

SU00740

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