80C32EBAA datasheet(49/62 Pages) PHILIPS

49 / 62 page

Philips Semiconductors

Product specification

80C52/80C54/80C58

CMOS single-chip 8-bit microcontrollers

1996 Aug 16

DC ELECTRICAL CHARACTERISTICS

Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5.0V ±10%; VSS = 0V

SYMBOL

PARAMETER

TEST

LIMITS

UNIT

SYMBOL

PARAMETER

TEST

CONDITIONS

MIN

TYP1

MAX

UNIT

VIL

Input low voltage

4.5V < VCC < 5.5V

–0.5

0.2VCC–0.1

VIH

Input high voltage (ports 0, 1, 2, 3, EA)

0.2VCC+0.9

VCC+0.5

VIH1

Input high voltage, XTAL1, RST

0.7VCC

VCC+0.5

VOL

Output low voltage, ports 1, 2, 38

VCC = 4.5V

IOL = 1.6mA2

0.4

VOL1

Output low voltage, port 0, ALE, PSEN8, 7

VCC = 4.5V

IOL = 3.2mA2

0.4

VOH

Output high voltage, ports 1, 2, 3 3

VCC = 4.5V

IOH = –30µA

VCC – 0.7

VOH1

Output high voltage (port 0 in external bus mode),

ALE9, PSEN3

VCC = 4.5V

IOH = –3.2mA

VCC – 0.7

IIL

Logical 0 input current, ports 1, 2, 3

VIN = 0.4V

–1

–50

µA

ITL

Logical 1-to-0 transition current, ports 1, 2, 36

VIN = 2.0V

See note 4

–650

µA

ILI

Input leakage current, port 0

0.45 < VIN < VCC – 0.3

±10

µA

ICC

Power supply current (see Figure 20):

Active mode @ 16MHz5

Idle mode @ 16MHz5

Power-down mode

See note 5

Tamb = 0 to +70°C

Tamb = –40 to +85°C

µA

RRST

Internal reset pull-down resistor

225

Ω

CIO

Pin capacitance10 (except EA)

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the (VCC–0.7) specification when the

address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when VIN is approximately 2V.

5. See Figures 21 through 24 for ICC test conditions.

Active Mode:

ICC = 0.9 × FREQ + 1.1;

Idle Mode:

ICC = 0.18 × FREQ +1.0; See Figure 20.

6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750µA.

7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin:

15mA (*NOTE: This is 85

°C specification.)

Maximum IOL per 8-bit port:

26mA

Maximum total IOL for all outputs:

71mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

test conditions.

9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification.

10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF

(except EA it is 25pF).

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