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80C32EBAA 数据表(PDF) 16 Page - NXP Semiconductors |
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80C32EBAA 数据表(HTML) 16 Page - NXP Semiconductors |
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16 / 62 page  Philips Semiconductors Product specification 80C32/87C52 CMOS single-chip 8-bit microcontrollers 1996 Aug 16 16 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 24MHz CLOCK VARIABLE CLOCK 33MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX MIN MAX UNIT 1/tCLCL 5 Oscillator frequency Speed versions : I :N 3.5 24 3.5 33 MHz tLHLL 5 ALE pulse width 43 2tCLCL–40 21 ns tAVLL 5 Address valid to ALE low 17 tCLCL–25 5 ns tLLAX 5 Address hold after ALE low 17 tCLCL–25 5 ns tLLIV 5 ALE low to valid instruction in 102 4tCLCL–65 56 ns tLLPL 5 ALE low to PSEN low 17 tCLCL–25 5 ns tPLPH 5 PSEN pulse width 80 3tCLCL–45 46 ns tPLIV 5 PSEN low to valid instruction in 65 3tCLCL–60 31 ns tPXIX 5 Input instruction hold after PSEN 0 0 0 ns tPXIZ 5 Input instruction float after PSEN 17 tCLCL–25 5 ns tAVIV 5 Address to valid instruction in 128 5tCLCL–80 72 ns tPLAZ 5 PSEN low to address float 10 10 10 ns Data Memory tRLRH 6, 7 RD pulse width 150 6tCLCL–100 82 ns tWLWH 6, 7 WR pulse width 150 6tCLCL–100 82 ns tRLDV 6, 7 RD low to valid data in 118 5tCLCL–90 62 ns tRHDX 6, 7 Data hold after RD 0 0 0 ns tRHDZ 6, 7 Data float after RD 55 2tCLCL–28 33 ns tLLDV 6, 7 ALE low to valid data in 183 8tCLCL–150 92 ns tAVDV 6, 7 Address to valid data in 210 9tCLCL–165 108 ns tLLWL 6, 7 ALE low to RD or WR low 75 175 3tCLCL–50 3tCLCL+50 41 141 ns tAVWL 6, 7 Address valid to WR low or RD low 92 4tCLCL–75 46 ns tQVWX 6, 7 Data valid to WR transition 12 tCLCL–30 0.3 ns tWHQX 6, 7 Data hold after WR 17 tCLCL–25 5 ns tQVWH 7 Data valid to WR high 162 7tCLCL–130 82 ns tRLAZ 6, 7 RD low to address float 0 0 0 ns tWHLH 6, 7 RD or WR high to ALE high 17 67 tCLCL–25 tCLCL+25 5 5 ns External Clock tCHCX 9 High time 17 17 tCLCL–tCLCX ns tCLCX 9 Low time 17 17 tCLCL–tCHCX ns tCLCH 9 Rise time 5 5 ns tCHCL 9 Fall time 5 5 ns Shift Register tXLXL 8 Serial port clock cycle time 505 12tCLCL 363 ns tQVXH 8 Output data setup to clock rising edge 283 10tCLCL–133 170 ns tXHQX 8 Output data hold after clock rising edge 3 2tCLCL–80 19 ns tXHDX 8 Input data hold after clock rising edge 0 0 0 ns tXHDV 8 Clock rising edge to input data valid 283 10tCLCL–133 170 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 8XC52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz “AC Electrial Characteristics”, page 15. |
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