ADP5054

Data Sheet

Rev. B | Page 28 of 31

TYPICAL APPLICATION CIRCUIT

OSCILLATOR

DDR

TERM.

LDO

INTERNAL

VREG

100mA

Q1

Q2

L1

1.0µH

L2

4.7µF

3.3µF

4.7µF

VREG

SYNC/MODE

VREG

ADP5054

RT 31.6kΩ

10Ω

4.99Ω

21.5kΩ

8.87kΩ

10kΩ

10kΩ

10kΩ

10kΩ

10.2kΩ

10.2kΩ

10.2kΩ

31.6kΩ

FB1

BST1

SW1

DL1

PGND

DL2

SW2

BST2

FB2

L3

BST3

SW3

FB3

PGND3

L4

BST4

SW4

FB4

PGND4

VREG

5.0V

PVIN1

PVIN2

COMP2

EN2

PVIN3

COMP3

EN3

PVIN4

COMP4

EN4

C1

1µF

C15

10µF

C15

2.2nF

C4

47µF

C5

47µF

C6

47µF

C7

47µF

C3

0.1µF

C9

0.1µF

C10

47µF

C11

47µF

C14

0.1µF

C16

0.1µF

C17

47µF

C13

47µF

12V

VOUT1

1.2V/6A

1.5V/2.5A

VOUT2

2.5V/2A

3.3V/2.5A

VOUT3

VOUT4

DDR3 MEMORY

FPGA

FPGA

AUXILIARY

VOLTAGE

FPGA

I/O BANK 3

BANK 0

BANK 1

BANK 2

FLASH MEMORY

PWRGD

VREG

EXPOSED PAD

C0

1µF

VDD

CFG34

CFG12

C12

10µF

C2

10µF

C8

10µF

2.2nF

2.2nF

2.2nF

COMP1

EN1

CHANNEL 1

BUCK

(2A/4A/6A)

CHANNEL 2

BUCK

(2A/4A/6A)

CHANNEL 3

BUCK

(2A)

CHANNEL 4

BUCK

(2A)

Figure 44. Typical Field Programmable Gate Array (FPGA) Application, 600 kHz Switching Frequency, Adjustable Output Model