ADP5054ACPZ-R7 datasheet(16/31 Pages) AD

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ADP5054

Data Sheet

Rev. B | Page 16 of 31

The frequency in each channel can be set to half the master

switching frequency set by the RT pin. This setting is configured

using the CFG12 and CFG34 pins (see Table 8 and Table 9). This

halving of the frequency is not recommended if the switching

frequency is less than 250 kHz.

Phase Shift

By default, the phase shift between Channel 1 and Channel 2 and

between Channel 3 and Channel 4 is 180° (see Figure 31). This

value provides the benefits of out-of-phase operation by reducing

the input ripple current and lowering the grounding noise.

CHANNEL 2

(½

fSW

OPTIONAL)

CHANNEL 1

(½

fSW

OPTIONAL)

CHANNEL 4

(½

fSW

OPTIONAL)

180° PHASE SHIFT

0° REFERENCE

CHANNEL 3

(½

fSW

OPTIONAL)

Figure 31. Phase Shift Diagram, Four Buck Regulators

SYNCHRONIZATION INPUT/OUTPUT

The switching frequency of the ADP5054 can be synchronized

to an external clock with a frequency range from 250 kHz to

2.0 MHz. The ADP5054 automatically detects the presence of

an external clock applied to the SYNC/MODE pin, and the

switching frequency transitions smoothly to the frequency of

the external clock. When the external clock signal stops, the

device automatically switches back to the internal clock and

continues to operate.

Note that the internal switching frequency set by the RT pin

must be programmed to a value that is close to the external

clock value for successful synchronization; the suggested

frequency difference is less than ±15% in typical applications.

The SYNC/MODE pin can be configured as a synchronization

clock output using CFG34 (see Table 9). A positive clock pulse

with a 50% duty cycle is generated at the SYNC/MODE pin

with a frequency equal to the internal switching frequency set

by the RT pin. There is a short delay time (approximately 15%

of tSW) from the generated synchronization clock to the

Channel 1 switching node.

Figure 32 shows two ADP5054 devices configured for frequency

synchronization mode: one ADP5054 device is configured as

the clock output to synchronize another ADP5054 device. It is

recommended that a 100 kΩ pull-up resistor be used to prevent

logic errors when the SYNC/MODE pin is left floating.

100kΩ

VREG

SYNC/MODE

Figure 32. Two ADP5054 Devices Configured for Synchronization Mode

In the configuration shown in Figure 32, the phase shift between

Channel 1 of the first ADP5054 device and Channel 1 of the

second ADP5054 device is 0° (see Figure 33).

CH3 5.00V BW

CH1 2.00V BW

CH2 5.00V BW

M400ns

A CH1

560mV

SW1

AT FIRST

ADP5054

SW1

AT SECOND

ADP5054

SYNC

OUTPUT

AT FIRST

ADP5054

Figure 33. Waveforms of Two ADP5054 Devices Operating in

Synchronization Mode

Table 8. CFG12 Configuration (Channel 1 and Channel 2)1

Channel 1

Channel 2

RTOP (kΩ)

RBOT (kΩ)

Soft Start (ms)

Frequency (kHz)

Soft Start (ms)

Frequency (kHz)

Parallel or Individual Operation

N/A

1 × fSW

Individual

100

600

½ × fSW

Individual

200

500

1 × fSW

½ × fSW

Individual

300

400

½ × fSW

1 × fSW

Individual

400

300

½ × fSW

N/A

Parallel

500

200

1 × fSW

N/A

Parallel

600

100

1 × fSW

N/A

Parallel

N/A

1 × fSW

Individual

N/A means not applicable.

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