ADP5054ACPZ-R7 datasheet(22/31 Pages) AD

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ADP5054

Data Sheet

Rev. B | Page 22 of 31

The output voltage ripple is determined by the effective series

resistance (ESR) of the output capacitor and its capacitance

value. Use the following equations to select a capacitor that can

meet the output ripple requirements:

RIPPLE

OUT

RIPPLE

OUT

∆

RIPPLE

OUT

ESR

∆

where:

ΔVOUT_RIPPLE is the allowable output voltage ripple.

RESR is the equivalent series resistance of the output capacitor.

Select the largest output capacitance given by COUT_UV, COUT_OV,

and COUT_RIPPLE to meet both load transient and output ripple

requirements.

The selected output capacitor voltage rating must be greater

than the output voltage. The minimum rms current rating of

the output capacitor is determined by the following equation:

RMS

OUT

∆

INPUT CAPACITOR SELECTION

The input decoupling capacitor attenuates high frequency noise

on the input and acts as an energy reservoir. This capacitor must be

a ceramic capacitor and must be placed close to the PVINx pins.

The loop composed of the input capacitor, the high-side NFET,

and the low-side NFET must be kept as small as possible. The

voltage rating of the input capacitor must be greater than the

maximum input voltage. The rms current rating of the input

capacitor must be larger than the following equation:

(

)

OUT

C RMS

−

where D is the duty cycle (D = VOUT/VIN).

LOW-SIDE POWER DEVICE SELECTION

Channel 1 and Channel 2 have integrated low-side MOSFET

drivers, which can drive the low-side N-channel MOSFETs

(NFETs). The selection of the low-side N-channel MOSFET

affects the buck regulator performance.

The selected MOSFET must meet the following requirements:

•

The drain source voltage (VDS) must be higher than 1.2 × VIN.

•

The drain current (ID) must be greater than 1.2 × ILIMIT_MAX,

where ILIMIT_MAX is the selected maximum current-limit

threshold.

•

The selected MOSFET can be fully turned on at VGS = 4.5 V.

•

Total gate charge (QG at VGS = 4.5 V) must be less than 35 nC.

Lower QG characteristics provide higher efficiency.

When the high-side MOSFET is turned off, the low-side MOSFET

supplies the inductor current. For low duty cycle applications,

the low-side MOSFET supplies the current for most of the

period. To achieve higher efficiency, it is important to select a

MOSFET with low on resistance. The power conduction loss for

the low-side MOSFET can be calculated using the following

equation:

PFET_LOW = IOUT2 × RDSON × (1 − D)

where:

RDSON is the on resistance of the low-side MOSFET.

D is the duty cycle (D = VOUT/VIN).

Table 12 lists recommended dual MOSFETs for various current-

limit settings. Ensure that the MOSFET can handle thermal

dissipation due to power loss.

Table 12. Recommended Dual MOSFETs

Vendor

Part No.

VDS

(V)

(A)

RDSON

(mΩ)

(nC)

Size

(mm)

Infineon

BSC072N03LD

7.2

5 × 6

BSO220N03MD

7.7

3.8

5 × 6

Vishay

Si4204DY

14.5

5 × 6

Si7232DN

16.4

3 × 3

SiA906EDJ

4.5

3.5

2 × 2

Fairchild

FDMA1024

5.0

5.2

2 × 2

FDMB3900

7.0

3 × 2

PROGRAMMING THE UVLO INPUT

The precision enable input can be used to program the UVLO

threshold of the input voltage, as shown in Figure 29. To limit

the degradation of the input voltage accuracy due to the internal

1 MΩ pull-down resistor tolerance, ensure that the bottom

resistor in the divider is not too large; a value of less than 50 kΩ

is recommended.

The precision turn-on threshold is 0.811 V. The resistive voltage

divider for the programmable VIN start-up voltage is calculated

as follows:

VIN_STARTUP = (0.8 nA + (0.811 V/RBOT_EN)) × (RTOP_EN + RBOT_EN)

where:

RTOP_EN is the resistor from VIN to ENx.

RBOT_EN is the resistor from ENx to ground.

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