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ADP5054ACPZ-R7 数据表(PDF) 3 Page - Analog Devices |
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ADP5054ACPZ-R7 数据表(HTML) 3 Page - Analog Devices |
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3 / 31 page  Data Sheet ADP5054 Rev. B | Page 3 of 31 DETAILED FUNCTIONAL BLOCK DIAGRAM + – Q1 UVLO1 PVIN1 SW1 BST1 DL1 VREG VREG DRIVER DRIVER PGND CONTROL LOGIC AND MOSFET DRIVER WITH ANTICROSS PROTECTION EN1 0.8V 1MΩ HICCUP AND LATCH-UP OCP COMP1 FB1 0.8V CLK1 SLOPE COMP CLK1 0.72V PWRGD1 ZERO CROSS + – + – CURRENT LIMIT SELECTION FREQ FOLDBACK + – + – CHANNEL 1—BUCK DUPLICATE CHANNEL 1 CHANNEL 2—BUCK CURRENT BALANCE EN2 COMP2 FB2 DL2 PVIN2 SW2 BST2 VID1 EA1 CMP1 RT OSCILLATOR SYNC/MODE FUNCTION DECODER CFG12 CFG34 VDD VREG INTERNAL REGULATOR PVIN1 VREG POWER-ON RESET PWRGD HOUSE-KEEPING LOGIC ACS1 + – Q3 Q4 UVLO3 PVIN3 SW3 BST3 VREG VREG DRIVER DRIVER PGND3 CONTROL LOGIC AND MOSFET DRIVER WITH ANTICROSS PROTECTION EN3 0.8V 1MΩ HICCUP AND LATCH-UP OCP COMP3 0.8V CLK3 SLOPE COMP CLK3 0.72V PWRGD3 ZERO CROSS + – + – FREQ FOLDBACK + – + – CHANNEL 3—BUCK DUPLICATE CHANNEL 3 CHANNEL 4—BUCK CURRENT BALANCE EN4 COMP4 FB4 PGND4 PVIN4 SW4 BST4 VID3 EA3 CMP3 ACS3 FB3 Figure 2. |
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