ADP5054ACPZ-R7 datasheet(17/31 Pages) AD

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Data Sheet

ADP5054

Rev. B | Page 17 of 31

Table 9. CFG34 Configuration (Channel 3, Channel 4, and SYNC/MODE)1

RTOP (kΩ)

RBOT (kΩ)

Channel 3

Channel 4

Parallel or Individual

Operation

SYNC/MODE

or Clock Out

Soft Start (ms)

Frequency (kHz)

Soft Start (ms)

Frequency (kHz)

N/A

1 × fSW

Individual

SYNC/MODE

100

600

½ × fSW

Individual

SYNC/MODE

200

500

½ × fSW

1 × fSW

Individual

SYNC/MODE

300

400

½ × fSW

N/A

Parallel

SYNC/MODE

400

300

1 × fSW

N/A

Parallel

SYNC/MODE

500

200

1 × fSW

N/A

Parallel

Clock out

(FPWM)

600

100

1 × fSW

Individual

Clock out

(FPWM)

N/A

1 × fSW

Individual

SYNC/MODE

N/A means not applicable.

SOFT START

The buck regulators in the ADP5054 include soft start circuitry

that ramps the output voltage in a controlled manner during

startup, thereby limiting the inrush current. The soft start time

is typically fixed at 2 ms for each buck regulator when the

CFG12 and CFG34 pins are tied to ground.

To set the soft start time to a value of 2 ms or 16 ms, connect a

resistor divider from the CFG12 pin or the CFG34 pin to the

VREG pin and ground (see Figure 34). This configuration may

be required to accommodate a specific start-up sequence or an

application with a large output capacitor.

LEVEL DETECTOR

AND DECODER

VREG

TOP

RESISTOR

BOTTOM

RESISTOR

CFG12

CFG34

Figure 34. Level Detector Circuit for Soft Start

The CFG12 pin can be used to program the soft start time, ½×

frequency setting, and parallel operation for Channel 1 and

Channel 2. The CFG34 pin can be used to program the soft

start time, ½× frequency setting, parallel operation, and clock

output feature for Channel 3 and Channel 4. Table 8 and Table 9

provide the values of the resistors needed to set the soft start time.

PARALLEL OPERATION

The ADP5054 supports two-phase parallel operation of Channel 1

and Channel 2 to provide a single output with up to 12 A of

current, and two-phase parallel operation of Channel 3 and

Channel 4 to provide a single output with up to 5 A of current.

To configure a two-phase single output in parallel operation,

take the following steps (see Figure 35):

•

Use the CFG12 pin (or CFG34 pin) to select parallel

operation as specified in Table 8 and Table 9.

•

Leave the COMP2 pin (or COMP4 pin) open.

•

Use the FB1 pin (or FB3 pin) to set the output voltage.

•

Connect the FB2 pin (or FB4 pin) to ground (FB2 or FB4

is ignored).

•

Connect the EN2 pin (or EN4 pin) to ground (EN2 or EN4

is ignored).

CHANNEL 1

BUCK

(4A)

CHANNEL 2

BUCK

(4A)

FB1

PVIN1

VOUT

(UP TO 12A)

VIN

EN1

EN2

COMP1

CFG12

SW1

FB2

SW2

PVIN2

COMP2

VREG

Figure 35. Parallel Operation for Channel 1 and Channel 2

The following considerations apply when two channels are

operated in parallel configuration.

•

The input voltages and current-limit settings for both

channels must be the same.

•

Both channels must be operated in FPWM mode.

Current balance in parallel configuration is well regulated by

the internal control loop. Figure 36 shows the Channel 1 and

Channel 2 typical current balance matching in parallel output

configuration. Figure 37 shows the Channel 3 and Channel 4

current balance matching in parallel output configuration.

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