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ADP5054ACPZ-R7 数据表(PDF) 27 Page - Analog Devices |
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ADP5054ACPZ-R7 数据表(HTML) 27 Page - Analog Devices |
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27 / 31 page  Data Sheet ADP5054 Rev. B | Page 27 of 31 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Good circuit board layout is essential to obtain the best performance from the ADP5054 (see Figure 43). Poor layout can affect the regulation and stability of the device, as well as the EMI and electromagnetic compatibility (EMC) performance. Refer to the following guidelines for a good PCB layout. • Place the input capacitor, inductor, MOSFET, output capacitor, and bootstrap capacitor close to the IC. • Use short, thick traces to connect the input capacitors to the PVINx pins, and use a dedicated power ground to connect the input and output capacitor grounds to minimize the connection length. • Use several high current vias, if required, to connect PVINx, PGNDx, or SWx to other power planes. • Use short, thick traces to connect the inductors to the SWx pins and the output capacitors. • Ensure that the high current loop traces are as short and wide as possible. The high current path is shown in Figure 42. • Maximize the amount of ground metal for the exposed pad, and use as many vias as possible on the component side to improve thermal dissipation. • Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. • Place the decoupling capacitors close to the VREG and VDD pins. • Place the frequency setting resistor close to the RT pin. • Place the feedback resistor divider close to the FBx pin. In addition, keep the FBx traces away from the high current traces and the switch node to avoid noise pickup. • Use 0402 or 0603 size resistors and capacitors to achieve the smallest possible footprint solution on boards where space is limited. VIN VOUT PVINx ENx GND BSTx SWx DLx FBx Figure 42. Typical Circuit with High Current Traces Shown in Blue C O U Tx - 47µF 6.3V /X5R 0805 C O U Tx - 47µF 6.3V /X 5R 0805 C O U Tx - 47µF 6.3V/X5R 0805 C O U Tx - 47µF 6.3V/X 5R 0805 R 0 4 0 2 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 ADP5054 C IN x - 10µF 25V/XR 5 0805 C IN x - 10µF 25V/X 5R 0805 C IN x - 10µF 25V/X 5R 0805 C IN x - 10µF 25V/XR 5 0805 SW 2 SW 2 B ST2 SW 2 PVIN2 D L2 PG N D D L1 PVIN 1 B ST1 SW 1 SW 1 SW 1 PVIN 2 EN 2 PVIN 2 C O M P4 FB 4 EN 4 B ST4 PG N D 4 SW 4 PVIN 4 PVIN 3 SW 3 PG N D 3 B ST3 VR EG PVIN 1 C O M P1 EN 1 PVIN 1 R T SYN C / M O D E FB 3 EN 3 C FG 34 C O M P3 C O U Tx - 47µF 6.3V/X5R 0805 C O U Tx - 47µF 6.3V/X5R 0805 R 0 4 0 2 VD D R 0 4 0 2 R 0 4 0 2 R 0 4 0 2 R 0 4 0 2 R 0 4 0 2 R 0 4 0 2 1 ADP5054 B P B D 4 4 4 4 N 3 D 3 3 3 3 M O D E C O M P2 FB 2 PW R G D SW 3 PG N D 3 SW 4 PG N D 4 C FG 12 FB 1 L3 L4 36 6 7 4 5 C IN x - 10µF 25V/ V X / 5R 0805 2 3 0805 8 9 C IN x - 10µF 25V/X 5R 0805 0805 0805 0805 C O U Tx 47µF C O U Tx - 47µF 6 3V /X / 5R C O U Tx - 47µF 6.3V/X 5R VOUT4 VOUT3 R 0 10 11 C O U T 47 F Dual FET 27 26 25 35 34 33 D l FET VOUT2 VOUT1 Figure 43. Typical PCB Layout for the ADP5054 |
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