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ADP5054

Data Sheet

Rev. B | Page 14 of 31

THEORY OF OPERATION

The ADP5054 is a micropower management unit that combines

four high performance buck regulators in a 48-lead LFCSP

package to meet demanding performance and board space

requirements. The device enables direct connection to high

input voltages of up to 15.5 V with no preregulators to make

applications simpler and more efficient.

BUCK REGULATOR OPERATIONAL MODES

PWM Mode

In pulse width modulation (PWM) mode, the buck regulators

in the ADP5054 operate at a fixed frequency; this frequency is

set by an internal oscillator that is programmed by the RT pin.

At the start of each oscillator cycle, the high-side MOSFET switch

turns on and sends a positive voltage across the inductor. The

inductor current increases until the current-sense signal

exceeds the peak inductor current threshold that turns off the

high-side MOSFET switch; this threshold is set by the error

amplifier output. During the high-side MOSFET off time, the

inductor current decreases through the low-side MOSFET

switch until the next oscillator clock pulse starts a new cycle.

The buck regulators in the ADP5054 regulate the output voltage

by adjusting the peak inductor current threshold.

PSM Mode

To achieve higher efficiency, the buck regulators in the ADP5054

smoothly transition to variable frequency, power savings mode

(PSM) operation when the output load falls below the PSM

current threshold. When the output voltage falls below regulation,

the buck regulator enters PWM mode for a few oscillator cycles

until the voltage increases to within regulation. During the idle

time between bursts, the MOSFET switch turns off, and the

output capacitor supplies all the output current.

The PSM mode comparator monitors the internal compensation

node, which represents the peak inductor current information.

The average PSM mode current threshold depends on the input

voltage (VIN), the output voltage (VOUT), the inductor, and the

output capacitor. Because the output voltage occasionally falls

below regulation and then recovers, the output voltage ripple in

PSM mode is larger than the ripple in forced PWM (FPWM)

mode under light load conditions.

Forced PWM and Automatic PWM/PSM Modes

The buck regulators can be configured to always operate in

forced PWM (FPWM) mode using the SYNC/MODE pin and

the I2C register. In FPWM mode, the regulator continues to

operate at a fixed frequency even when the output current is

below the PWM/PSM threshold. In PWM mode, efficiency is

lower compared to PSM mode under light load conditions. The

low-side MOSFET remains on when the inductor current falls

to less than 0 A, causing the ADP5054 to enter continuous

conduction mode (CCM).

The buck regulators can be configured to operate in automatic

PWM/PSM mode using the SYNC/MODE pin. In automatic

PWM/PSM mode, the buck regulators operate in either PWM

mode or PSM mode, depending on the output current. When

the average output current falls below the PWM/PSM threshold,

the buck regulator enters PSM mode; in PSM mode, the regulator

operates with a reduced switching frequency to maintain high

efficiency. The low-side MOSFET turns off when the output

current reaches 0 A, causing the regulator to operate in

discontinuous mode (DCM).

The user can alternate between FPWM mode and automatic

PWM/PSM mode during operation. The flexible configuration

capability during device operation enables efficient power

management.

When a logic high level is applied to the SYNC/MODE pin (or

when SYNC/MODE is configured as a clock input or output), the

operational mode of all four buck regulators is set for forced PWM

mode. When a logic low level is applied to the SYNC/MODE pin,

the operational mode of all four buck regulators is automatic

PWM/PSM mode.

Table 7 describes the function of the SYNC/MODE pin in

setting the operational mode of the device.

Table 7. Configuring the Mode of Operation Using the

SYNC/MODE Pin

Mode of Operation for All Channels

High

Forced PWM mode

Clock In/Out

Forced PWM mode

Low

Automatic PWM/PSM mode

ADJUSTABLE AND FIXED OUTPUT VOLTAGE

The ADP5054 provides adjustable and fixed output voltage settings

via the factory fuse. For the adjustable output settings, use an

external resistor divider to set the desired output voltage via the

feedback reference voltage (0.8 V for Channel 1 to Channel 4).

For the fixed output settings, the feedback resistor divider is

built into the ADP5054, and the feedback pin (FBx) must be

tied directly to the output. Each buck regulator channel can be

programmed for a specific output voltage. Table 14 lists the

fixed output ranges configured by the factory fuse.

If a different output voltage range is required, contact your local

Analog Devices, Inc., sales or distribution representative.

INTERNAL REGULATORS (VREG AND VDD)

The internal VREG regulator in the ADP5054 provides a stable

5.0 V power supply for the bias voltage of the MOSFET drivers.

The internal VDD regulator in the ADP5054 provides a stable

3.3 V power supply for the internal control circuits. One 1.0 µF

ceramic capacitor must be connected between VREG and

ground, and another 1.0 µF ceramic capacitor must be

connected between VDD and ground.

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