Data Sheet

ADP5054

Rev. B | Page 9 of 31

Pin No.

Mnemonic

Description

39

EN1

Enable Input for Channel 1. Use an external resistor divider to set the turn-on threshold.

40

COMP1

Error Amplifier Output for Channel 1. Connect an RC network from this pin to ground.

41

FB1

Feedback Sensing Input for Channel 1.

42

RT

Connect a resistor from RT to ground to program the switching frequency from 250 kHz to 2 MHz.

43

VDD

Output of the Internal 3.3 V Linear Regulator. Connect a 1.0 µF ceramic capacitor between this pin and ground.

44

SYNC/MODE

Synchronization Input/Output (SYNC). To synchronize the switching frequency of the device to an external

clock, connect this pin to an external clock with a frequency from 250 kHz to 2.0 MHz. This pin can also be

configured as a synchronization output via the CFG34 pin configuration.

Forced PWM or Automatic PWM/PSM Selection Pin (MODE). When this pin is logic high, each channel works in

forced PWM or automatic PWM/PSM mode. When this pin is logic low, all channels operate in automatic

PWM/PSM mode.

45

VREG

Output of the Internal 5.0 V Linear Regulator. Connect a 1.0 µF ceramic capacitor between this pin and ground.

46

FB3

Feedback Sensing Input for Channel 3.

47

COMP3

Error Amplifier Output for Channel 3. Connect an RC network from this pin to ground.

48

EN3

Enable Input for Channel 3. Use an external resistor divider to set the turn-on threshold.

49

EPAD

Exposed Pad (Analog Ground). The exposed pad must be connected and soldered to an external ground plane.