ADP5054

Data Sheet

Rev. B | Page 8 of 31

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED AND

SOLDERED TO AN EXTERNAL GROUND PLANE.

BST4

PGND4

PGND4

SW4

SW4

PVIN4

PVIN3

SW3

SW3

PGND3

PGND3

BST3

PVIN1

SW1

SW1

SW1

BST1

DL1

PGND

DL2

BST2

SW2

SW2

SW2

1

2

3

4

5

6

7

ADP5054

TOP VIEW

(Not to Scale)

25

26

27

28

29

30

31

32

33

34

35

36

8

9

10

11

12

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

BST3

High-Side FET Driver Power Supply for Channel 3.

2, 3

PGND3

Power Ground for Channel 3.

4, 5

SW3

Switching Node Output for Channel 3.

6

PVIN3

Power Input for Channel 3. Connect a bypass capacitor between this pin and ground.

7

PVIN4

Power Input for Channel 4. Connect a bypass capacitor between this pin and ground.

8, 9

SW4

Switching Node Output for Channel 4.

10, 11

PGND4

Power Ground for Channel 4.

12

BST4

High-Side FET Driver Power Supply for Channel 4.

13

CFG34

Connect a resistor divider from this pin to VREG and ground to configure the different functionalities for Channel 3

and Channel 4, including the soft start timer, ½× frequency, parallel operation, and SYNC clock output features.

14

EN4

Enable Input for Channel 4. Use an external resistor divider to set the turn-on threshold.

15

COMP4

Error Amplifier Output for Channel 4. Connect an RC network from this pin to ground.

16

FB4

Feedback Sensing Input for Channel 4.

17

PWRGD

Power-Good Signal Output. This open-drain output is the power-good signal for the selected channels.

18

CFG12

Connect a resistor divider from this pin to VREG and ground to configure the different functionalities for Channel 1

and Channel 2, including the soft start timer, ½× frequency, and parallel operation features.

19

FB2

Feedback Sensing Input for Channel 2.

20

COMP2

Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground.

21

EN2

Enable Input for Channel 2. Use an external resistor divider to set the turn-on threshold.

22, 23, 24

PVIN2

Power Input for Channel 2. Connect a bypass capacitor between this pin and ground.

25, 26, 27

SW2

Switching Node Output for Channel 2.

28

BST2

High-Side FET Driver Power Supply for Channel 2.

29

DL2

Low-Side FET Gate Driver for Channel 2. Connect a resistor from this pin to ground to program the current-limit

threshold for Channel 2.

30

PGND

Power Ground for Channel 1 and Channel 2.

31

DL1

Low-Side FET Gate Driver for Channel 1. Connect a resistor from this pin to ground to program the current-limit

threshold for Channel 1.

32

BST1

High-Side FET Driver Power Supply for Channel 1.

33, 34, 35

SW1

Switching Node Output for Channel 1.

36, 37, 38

PVIN1

Power Input for the Internal Linear Regulator and the Channel 1 Buck Regulator. Connect a bypass capacitor

between this pin and ground.