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Data Sheet

ADP5054

Rev. B | Page 15 of 31

The internal VREG and VDD regulators are active as long as

PVIN1 is available. The internal VREG regulator can provide a

total load of 150 mA, including the MOSFET driving current.

The current-limit circuit is included in the VREG regulator to

protect the circuit when the device is heavily loaded.

Note that the VDD regulator is for internal circuit use and is

not recommended for other purposes.

SEPARATE SUPPLY APPLICATIONS

The ADP5054 supports separate input voltages for the four

buck regulators, meaning the input voltages for the four buck

regulators can be connected to different supply voltages. The

PVIN1 voltage provides the power supply for the internal

regulators and the control circuitry. Therefore, if the user plans

to use separate supply voltages for the buck regulators, the

PVIN1 voltage must be above the UVLO threshold before the

other channels begin to operate.

Note that precision enabling can be used to monitor the PVIN1

voltage and to delay the startup of the outputs to ensure that

PVIN1 is high enough to support the outputs in regulation (see

the Precision Enabling section).

The ADP5054 supports cascading supply operations for the

four buck regulators. As shown in Figure 28, PVIN2, PVIN3,

and PVIN4 are powered from the Channel 1 output. In this

configuration, the Channel 1 output voltage must be higher

than the UVLO threshold for PVIN2, PVIN3, and PVIN4.

PVIN1

BUCK 1

BUCK 2

VOUT1

PVIN2

PVIN4

VOUT2 TO VOUT4

VIN

Figure 28. Cascading Supply Application

LOW-SIDE DEVICE SELECTION

The buck regulators in Channel 1 and Channel 2 integrate 6 A

high-side power MOSFETs and low-side MOSFET drivers. The

N-channel MOSFETs selected for use with the ADP5054 must

be able to work with the synchronized buck regulators. In

general, use a low RDS(ON) N-channel MOSFET to achieve higher

efficiency; dual MOSFETs in one package (for both Channel 1

and Channel 2) are recommended to save space on the printed

circuit board (PCB). For more information, see the Low-Side

Power Device Selection section.

BOOTSTRAP CIRCUITRY

Each buck regulator in the ADP5054 has an integrated boot

regulator. The boot regulator requires a 0.1 µF ceramic

capacitor (X5R or X7R) between the BSTx and SWx pins to

provide the gate drive voltage for the high-side MOSFET.

ACTIVE OUTPUT DISCHARGE SWITCH

Each buck regulator in the ADP5054 integrates a discharge

switch from the switching node to ground. This switch is turned

on when its associated regulator is disabled, which helps to

discharge the output capacitor quickly. The typical value of the

discharge switch is 120 Ω for Channel 1 to Channel 4.

PRECISION ENABLING

The ADP5054 has an enable control pin for each regulator,

including the LDO regulator. Each enable control pin (ENx)

features a precision enable circuit with a 0.811 V reference

voltage. When the voltage at the ENx pin is greater than 0.811 V,

the regulator is enabled. When the ENx pin voltage falls below

0.72 V, the regulator is disabled. An internal 1 MΩ pull-down

resistor prevents errors if the ENx pin is left floating.

The precision enable threshold voltage allows easy sequencing

of channels within the device, as well as sequencing between the

ADP5054 and other input/output supplies. The ENx pin can

also be used as a programmable UVLO input using a resistor

divider (see Figure 29).

0.811V

DEGLITCH

TIMER

INTERNAL

ENABLE

ENx

1MΩ

INPUT/OUTPUT

VOLTAGE

Figure 29. Precision Enable Diagram for One Channel

OSCILLATOR

The switching frequency (fSW) of the ADP5054 can be set to a

value from 250 kHz to 2.0 MHz by connecting a resistor from

the RT pin to ground. The value of the RT resistor can be

calculated as follows:

RRT (kΩ) = [14,822/fSW (kHz)]1.081

Figure 30 shows the typical relationship between fSW and the RT

resistor. The adjustable frequency allows users to make decisions

based on the trade-off between efficiency and the size of the

solution.

200

400

600

800

1000

1200

1400

1600

1800

2000

2200

RT RESIST

OR (kΩ)

Figure 30. Switching Frequency vs. RT Resistor

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