USB3370 datasheet(23/75 Pages) MICROCHIP

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DS00001915B-page 23

USB3370

Note 5-3

VDDIO

must be present for ULPI pins to tri-state.

5.6.4

START-UP

The power on default state of the USB3370 is ULPI Synchronous mode. The USB3370 requires the following conditions

to begin operation: the power supplies must be stable, the REFCLK must be present and the RESETB pin must be high.

After these conditions are met, the USB3370 will begin ULPI operation that is described in Section 6.0.

Figure 5-5 below shows a timing diagram to illustrate the start-up of the USB3370. At T0, the supplies are stable and

the USB3370 is held in reset mode. At T1, the Link drives RESETB high after the REFCLK has started. The RESETB

pin may be brought high asynchronously to REFCLK. Once, the 3.3V and 1.8V internal supplies become stable the

USB3370 will apply the 15Kohm pull downs to the data bus and assert DIR until the internal PLL has locked. After the

PLL has locked, the USB3370 will check that the Link has de-asserted STP and at T2 it will de-assert DIR and begin

ULPI operation.

The ULPI bus will be available as shown in Figure 5-5 in the time defined as TSTART given in Table 4-2. If the REFCLK

signal starts after the RESETB pin is brought high, then time T0 will begin when REFCLK starts. TSTART also assumes

that the Link has de-asserted STP. If the Link has held STP high the USB3370 will hold DIR high until STP is de-

asserted. When the LINK de-asserts STP, it must be ready drive the ULPI data bus to idle (00h) for a minimum of one

clock cycle after DIR de-asserts.

TABLE 5-2:

OPERATING MODE VS. POWER SUPPLY CONFIGURATION

VBAT

VDDIO

RESETB

Operating Modes Available

Powered Off

RESET Mode. (Note 5-3)

Full USB operation as described in Section 6.0.

FIGURE 5-5:

ULPI START-UP TIMING

DIR

RESETB

STP

TSTART

REFCLK

SUPPLIES

STABLE

PHY Drives Idle

DATA[7:0]

REFCLK valid

PHY Tri-States

PHY Drives High

LINK Drives Low

RXCMD

IDLE

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