USB3370 datasheet(41/75 Pages) MICROCHIP

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DS00001915B-page 41

USB3370

6.3.1.1.3

HS CHIRP Linestate Definition

There is also a third use of Linestate in HS Chirp where when the Host and Peripheral negotiate the from FS mode to

HS mode. While the transitions from K to J or SE0 are communicated to the Link through the Linestate information.

6.3.2

USB RECEIVER

The USB3370 ULPI receiver fully supports HS, FS, and LS transmit operations. In all three modes the receiver detects

the start of packet and synchronizes to the incoming data packet. In the ULPI protocol, a received packet has the priority

and will immediately follow register reads and RXCMD transfers. Figure 6-8 shows a basic USB packet received by the

USB3370 over the ULPI interface.

In Figure 6-8 the PHY asserts DIR to take control of the data bus from the Link. The assertion of DIR and NXT in the

same cycle contains additional information that Rxactive has been asserted. When NXT is de-asserted and DIR is

asserted, the RXCMD data is transferred to the Link. After the last byte of the USB receive packet is transferred to the

PHY, the linestate will return to idle.

The ULPI Full Speed receiver operates according to the UTMI / ULPI specification. In the Full Speed case, the NXT

signal will assert only when the Data bus has a valid received data byte. When NXT is low with DIR high, the RXCMD

is driven on the data bus.

In Full Speed, the USB3370 will not issue a Rxactive de-assertion in the RXCMD until the DP/DM linestate transitions

to idle. This prevents the Link from violating the two Full Speed bit times minimum turn around time.

TABLE 6-6:

USB LINESTATE DECODING IN HS CHIRP MODE

Linestate[1:0]

DP SE RX

DM SE RX

State

SE0

HS Squelch asserted

HS Squelch de-asserted & HS

differential Receiver = 1

HS Squelch de-asserted & HS

differential Receiver = 0

SE1

Invalid State

FIGURE 6-8:

ULPI RECEIVE IN SYNCHRONOUS MODE

DIR

CLK

DATA[7:0]

STP

NXT

Rxd

Cmd

Idle

Turn

around

PID

Rxd

Cmd

Turn

around

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