USB3370 datasheet(34/75 Pages) MICROCHIP

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USB3370

DS00001915B-page 34

 2012 - 2015 Microchip Technology Inc.

RxEndDelay maximum allowed by the UTMI+/ULPI for 8-bit data is 63 Hi-Speed clocks. USB3370 uses a low latency

Hi-Speed receiver path to lower the RxEndDelay to 43 Hi-Speed clocks. This low latency design gives the Link more

cycles to make decisions and reduces the Link complexity. This is the result of the “wrapper less” architecture of the

USB3370. This low RxEndDelay should allow legacy UTMI Links to use a “wrapper” to convert the UTMI+ interface to

a ULPI interface.

In Figure 6-1, a single ULPI Protocol Block decodes the ULPI 8-bit bi-directional bus when the Link addresses the PHY.

The Link must use the DIR output to determine direction of the ULPI data bus. The USB3370 is the “bus arbitrator”. The

ULPI Protocol Block will route data/commands to the transmitter or the ULPI register array.

6.1.1

ULPI INTERFACE SIGNALS

The UTMI+ Low Pin Interface (ULPI) uses a 12-pin interface to connect a USB Transceiver to an external Link. The

reduction of external pins, relative to UTMI+, is accomplished implementing the relatively static configuration pins (i.e.

xcvrselect[1:0], termselect, opmode[1:0], and DpPullDown DmPulldown) as an internal register array.

An 8-bit bi-directional data bus clocked at 60MHz allows the Link to access this internal register array and transfer USB

packets to and from the PHY. The remaining 3 pins function to control the data flow and arbitrate the data bus.

Direction of the 8-bit data bus is controlled by the DIR output from the PHY. Another output, NXT, is used to control

data flow into and out of the device. Finally, STP, which is in input to the PHY, terminates transfers and is used to start

up and resume from Low Power Mode.

The ULPI Interface signals are described below in Table 6-1.

USB3370 implements a Single Data Rate (SDR) ULPI interface with all data transfers happening on the rising edge of

the 60MHz ULPI Clock while operating in Synchronous Mode. The direction of the data bus is determined by the state

of DIR. When DIR is high, the PHY is driving DATA[7:0]. When DIR is low, the Link is driving DATA[7:0].

Each time DIR changes, a “turn-around” cycle occurs where neither the Link nor PHY drive the data bus for one clock

cycle. During the “turn-around“cycle, the state of DATA[7:0] is unknown and the PHY will not read the data bus.

Because USB uses a bit-stuffing encoding, some means of allowing the PHY to throttle the USB transmit data is needed.

The ULPI signal NXT is used to request the next byte to be placed on the data bus by the Link.

The ULPI interface supports the two basic modes of operation: Synchronous Mode and Asynchronous Mode. Asynchro-

nous Mode includes Low Power Mode, the Serial Modes, and Carkit Mode. In Synchronous Mode, all signals change

synchronously with the 60MHz ULPI clock. In asynchronous modes the clock is off and the ULPI bus is redefined to

bring out the signals required for that particular mode of operations. The description of synchronous Mode is described

in the following sections while the descriptions of the asynchronous modes are described in Section 6.5, Section 6.6,

and Section 6.7.

TABLE 6-1:

ULPI INTERFACE SIGNALS

Signal

Direction

Description

CLK

I/O

60MHz ULPI clock. All ULPI signals are driven synchronous to the rising edge of

this clock. This clock can be either driven by the PHY or the Link as described in

Section 5.5.1

DATA[7:0]

I/O

8-bit bi-directional data bus. Bus ownership is determined by DIR. The Link and PHY

initiate data transfers by driving a non-zero pattern onto the data bus. ULPI defines

interface timing for a single-edge data transfers with respect to rising edge of the

ULPI clock.

DIR

OUT

Controls the direction of the data bus. When the PHY has data to transfer to the

Link, it drives DIR high to take ownership of the bus. When the PHY has no data to

transfer it drives DIR low and monitors the bus for commands from the Link. The

PHY will pull DIR high whenever the interface cannot accept data from the Link,

such as during PLL start-up.

STP

The Link asserts STP for one clock cycle to stop the data stream currently on the

bus. If the Link is sending data to the PHY, STP indicates the last byte of data was

on the bus in the previous cycle.

NXT

OUT

The PHY asserts NXT to throttle the data. When the Link is sending data to the PHY,

NXT

indicates when the current byte has been accepted by the PHY. The Link

places the next byte on the data bus in the following clock cycle.

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