USB3370 datasheet(47/75 Pages) MICROCHIP

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DS00001915B-page 47

USB3370

When the USB3370 sends a RXCMD the Link is required to drive the data bus back to idle at the end of the turn around

cycle. If the Link does not drive the databus to idle the USB3370 may take the information on the data bus as a TXCMD

and transmit data on DP and DM until the Link asserts stop. If the ID pin is floated the last RXCMD from the USB3370

will remain on the bus after DIR is de-asserted and the USB3370 will take this in as a TXCMD.

A Link should be designed to have the default POR state of the STP output high and the data bus tri-stated. The

USB3370 has weak pull-downs on the data bus to prevent these inputs from floating when not driven. These resistors

are only used to prevent the ULPI interface from floating during events when the link ULPI pins may be tri-stated. The

strength of the pull down resistors can be found in Table 4-4. The pull downs are not strong enough to pull the data bus

low after a ULPI RXCMD, the Link must drive the data bus to idle after DIR is de-asserted.

In some cases, a Link may be software configured and not have control of its STP pin until after the PHY has started.

In this case, the USB3370 has in internal pull-up on the STP input pad which will pull STP high while the Link’s STP

output is tri-stated. The STP pull-up resistor is enabled on POR and can be disabled by setting the InterfaceProtectDis-

able

bit 7 of the Interface Control register.

The STP pull-up resistor will pull-up the Link’s STP input high until the Link configures and drives STP high. After the

Link completes its start-up, STP can be synchronously driven low.

A Link design which drives STP high during POR can disable the pull-up resistor on STP by setting InterfaceProtect-

Disable

bit to 1. A motivation for this is to reduce the suspend current. In Low Power Mode, STP is held low, which would

draw current through the pull-up resistor on STP.

6.5.4.2

Warm Reset

Designers should also consider the case of a warm restart of a Link with a PHY in Low Power Mode. After the PHY

enters Low Power Mode, DIR is asserted and the clock is stopped. The USB3370 looks for STP to be asserted to re-

start the clock and then resume normal synchronous operation.

Should the USB3370 be suspended in Low Power Mode, and the Link receives a hardware reset, the PHY must be able

to recover from Low Power Mode and start its clock. If the Link asserts STP on reset, the PHY will exit Low Power Mode

and start its clock.

If the Link does not assert STP on reset, the interface protection pull-up can be used. When the Link is reset, its STP

output will tri-state and the pull-up resistor will pull STP high, signaling the PHY to restart its clock.

6.5.5

MINIMIZING CURRENT IN LOW POWER MODE

In order to minimize the suspend current in Low Power Mode, the VBUS and ID comparators can be disabled to reduce

suspend current. In Low Power Mode, the VbusVld and SessEnd comparators are not needed and can be disabled by

clearing the associated bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. By dis-

abling the interrupt in BOTH the rise and fall registers, the SessEnd and VbusVld comparators are turned off. The

IdFloatRise

and IdFloatFall bits in Carkit Interrupt Enable register should also be disabled if they were set. When exiting

Low Power Mode, the Link should immediately re-enable the VbusVld and SessEnd comparators if host or OTG func-

tionality is required.

In addition to disabling the OTG comparators in Low Power Mode, the Link may choose to disable the Interface Protect

Circuit. By setting the InterfaceProtectDisable bit high in the Interface Control register, the Link can disable the pull-up

resistor on STP. When RESETB is low the Interface Protect Circuit will be disabled.

6.6

Full Speed/Low Speed Serial Modes

The USB3370 includes two serial modes to support legacy Links which use either the 3pin or 6pin serial format. To enter

either serial mode, the Link will need to write a 1 to the 6-pin FsLsSerialMode or the 3-pin FsLsSerialMode bits in the

Interface control register. Serial Mode may be used to conserve power when attached to a device that is not capable of

operating in Hi-Speed.

The serial modes are entered in the same manner as the entry into Low Power Mode. The Link writes the Interface

Control register bit for the specific serial mode. The USB3370 will assert DIR and shut off the clock after at least five

clock cycles. Then the data bus goes to the format of the serial mode selected. Before entering Serial Mode the Link

must set the ULPI transceiver to the appropriate mode as defined in Table 5-1.

In ULPI Clock Output Mode, the PHY will shut off the 60MHz clock to conserve power. Should the Link need the 60MHz

clock to continue during the serial mode of operation, the ClockSuspendM bit[3] of the Interface Control Register should

be set before entering a serial mode. If set, the 60 MHz clock will be present during serial modes.

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