USB3370 datasheet(17/75 Pages) MICROCHIP

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DS00001915B-page 17

USB3370

5.0

ARCHITECTURE OVERVIEW

The USB3370 consists of the blocks shown in the diagram below.

5.1

ULPI Digital Operation and Interface

This section of the USB3370 is covered in detail in Section 6.0, "ULPI Operation".

5.2

USB 2.0 Hi-Speed Transceiver

The blocks in the lower left-hand corner of Figure 6-1 interface to the DP/DM pins.

5.2.1

USB TRANSCEIVER

The USB3370 transceiver includes a Universal Serial Bus Specification Rev 2.0 compliant receiver and transmitter. The

DP/DM signals in the USB cable connect directly to the receivers and transmitters.

The receiver consists of receivers for HS and FS/LS mode. Depending on the mode, the selected receiver provides the

serial data stream through the multiplexer to the RX Logic block. For HS mode support, the HS RX block contains a

squelch circuit to insure that noise is not interpreted as data. The RX block also includes a single-ended receiver on

each of the data lines to determine the correct FS linestate.

Data from the Link is encoded, bit stuffed, serialized and transmitted onto the USB cable by the transmitter. Separate

differential FS/LS and HS transmitters are included to support all modes.

The USB3370 TX block meets the HS signaling level requirements in the USB 2.0 Specification when the PCB traces

from the DP and DM pins to the USB connector are correctly designed. In some systems the proper 90 ohm differential

impedance can not be maintained and it may be desirable to compensate for loss by adjusting the HS transmitter ampli-

tude and this HS squelch threshold. The PHYBoost bits in the HS Compensation Register may be configured to adjust

the HS transmitter amplitude at the DP and DM pins. The VariSense bits in the HS Compensation Register can also be

used to lower the squelch threshold to compensate for losses on the PCB.

To ensure proper operation of the USB transceiver the settings of Table 5-1 must be followed.

FIGURE 5-1:

USB3370 SYSTEM DIAGRAM

BIAS

Integrated

Low Jitter

PLL

RBIAS

DIR

NXT

STP

CLKOUT

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA0

DATA1

REFCLK / XI

VDDIO

VBAT

VDD33

VBUS

LDO

ULPI

Digitial

HS/FS/LS

TX Encoding

HS/FS/LS

RX Decoding

RESETB

IdGnd

IdFloat

Rid Value

SessEnd

SessValid

VbusValid

OVP

CPEN_N

VDD33

LDO

VDD18

EXTVBUS

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