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USB3370 数据表(PDF) 45 Page - Microchip Technology

部件名 USB3370
功能描述  Enhanced Single Supply Hi-Speed USB ULPI Transceiver
PDF  75 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

USB3370 数据表(HTML) 45 Page - Microchip Technology

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2012 - 2015 Microchip Technology Inc.
DS00001915B-page 45
USB3370
While in Low Power Mode, the Data interface is redefined so that the Link can monitor Linestate and the VBUS voltage.
In Low Power Mode DATA[3:0] are redefined as shown in Table 6-7. Linestate[1:0] is the combinational output of the
Single-Ended Receivers. The “int” or interrupt signal indicates an unmasked interrupt has occurred. When an unmasked
interrupt or linestate change has occurred, the Link is notified and can determine if it should wake-up the PHY.
Note 6-1
LineState: These signals reflect the current state of the Full-Speed single ended receivers.
LineState[0] directly reflects the current state of DP. LineState[1] directly reflects the current state of
DM
. When DP=DM=0 this is called "Single Ended Zero" (SE0). When DP=DM=1, this is called
"Single Ended One" (SE1).
An unmasked interrupt can be caused by the following comparators changing state: VbusVld, SessVld, SessEnd, and
IdGnd. If any of these signals change state during Low Power Mode and the bits are enabled in either the USB Interrupt
Enable Rising or USB Interrupt Enable Falling registers, DATA[3] will assert. During Low Power Mode, the VbusVld and
SessEnd comparators can have their interrupts masked to lower the suspend current as described in Section 6.5.5.
While in Low Power Mode, the Data bus is driven asynchronously because all of the PHY clocks are stopped during
Low Power Mode.
FIGURE 6-11:
ENTERING LOW POWER MODE FROM SYNCHRONOUS MODE
TABLE 6-7:
INTERFACE SIGNAL MAPPING DURING LOW POWER MODE
Signal
Maps To
Direction
Description
linestate[0]
DATA[0]
OUT
Combinatorial LineState[0] driven directly by the Full-Speed single
ended receiver. Note 6-1
linestate[1]
DATA[1]
OUT
Combinatorial LineState[1] driven directly by the Full-Speed single
ended receiver. Note 6-1
reserved
DATA[2
]
OUT
Driven Low
int
DATA[3]
OUT
Active high interrupt indication. Must be asserted whenever any
unmasked interrupt occurs.
reserved
DATA[7:4]
OUT
Driven Low
DIR
CLK
DATA[7:0]
STP
NXT
TXD CMD
(reg write)
Idle
Reg Data[n]
Idle
T0
T1
T2
T3
T5
T4
T6
T10
Turn
Around
Low Power Mode
SUSPENDM
(ULPI Register Bit)
...



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