USB3370 datasheet(19/75 Pages) MICROCHIP

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DS00001915B-page 19

USB3370

Note 1:

This is equivalent to Table 40, Section 4.4 of the ULPI 1.1 specification.

USB3370 does not support operation as an upstream hub port. See Section 6.4.1.3.

Note 5-1

When RESETB = 0 The HS termination will tri-state the USB drivers

Note 5-2

The transceiver operation is not guaranteed in a combination that is not defined.

The USB3370 uses the 27% resistor ECN resistor tolerances. The resistor values are shown in Table 4-5.

5.3

Bias Generator

This block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the

analog circuits. This block requires an external 10K

Ω, 1% tolerance, reference resistor connected from RBIAS to

ground. This resistor should be placed as close as possible to the USB3370 to minimize the trace length. The nominal

voltage at RBIAS is 0.8V +/- 10% and therefore the resistor will dissipate approximately 80

μW of power.

5.4

Crystal Reference Support

The USB3370 provides support for a crystal to provide the reference frequency required by the device in place of a clock

oscillator. The crystal should be connected to the REFCLK/XI and XO pins. If a clock oscillator is used in place of a

crystal, it should be driven into the REFCLK/XI pin, and the XO pin should be left floating. Proper care should be taken

to ensure that a crystal is selected with appropriate power dissipation characteristics.

5.5

Integrated Low Jitter PLL

The USB3370 uses an integrated low jitter phase locked loop (PLL) to provide a clean 480MHz clock required for HS

USB signal quality. This clock is used by the PHY during both transmit and receive. The USB3370 PLL requires an accu-

rate frequency reference to be driven on the REFCLK pin.

5.5.1

REFCLK FREQUENCY SELECTION

The USB3370 PLL is designed to operate in one of two reference clock modes. In the first mode, the 60MHz ULPI clock

is driven on the REFCLK pin. In the second mode a reference clock is driven on the REFCLK pin. The Link is driving

the ULPI clock, in the first mode, and this is referred to as ULPI Clock Input Mode. In the second mode, the USB3370

generates the ULPI clock, and this is referred to as ULPI Clock Output Mode.

During start-up, the USB3370 monitors the CLKOUT pin. If a connection to VDDIO is detected, the USB3370 is config-

ured for a 60MHz ULPI reference clock driven on the REFCLK pin. Section 5.5.1.1 and Section 5.5.1.2 describe how

to configure the USB3370 for either ULPI Clock Input Mode or ULPI Clock Output Mode.

OTG device, Peripheral FS

01b

00b

OTG device, Peripheral HS/FS Suspend

01b

00b

OTG device, Peripheral HS/FS Resume

01b

10b

OTG device, Peripheral Test J/Test K

00b

10b

Charger Detection

Connect Detect

01b

00b0b

0b0b0b1b0b

Any combination not defined above, Note 5-

TABLE 5-1:

DP/DM TERMINATION VS. SIGNALING MODE (CONTINUED)

Signaling Mode

ULPI Register Settings

USB3370 Termination Resistor

Settings

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