USB3370 datasheet(37/75 Pages) MICROCHIP

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DS00001915B-page 37

USB3370

6.2.3

ULPI REGISTER READ

A ULPI register read operation is given in Figure 6-5. The Link drives a TX CMD byte with DATA[7:6] = 11h for a register

read. DATA[5:0] of the ULPI TX command bye contain the register address.

At T0, the Link will place the TX CMD on the data bus. At T2, the PHY will bring NXT high, signaling the Link it is ready

to accept the data transfer. At T3, the PHY reads the TX CMD, determines it is a register read, and asserts DIR to gain

control of the bus. The PHY will also de-assert NXT. At T4, the bus ownership has transferred back to the PHY and the

FIGURE 6-4:

ULPI EXTENDED REGISTER WRITE IN SYNCHRONOUS MODE

FIGURE 6-5:

ULPI REGISTER READ IN SYNCHRONOUS MODE

DIR

CLK

DATA[7:0]

STP

NXT

TXD CMD

(extended reg write)

Idle

Reg Data[n]

Idle

ULPI Register

Reg Data [n-1]

Reg Data [n]

Extended

address

DIR

CLK

DATA[7:0]

STP

NXT

TXD CMD

reg read

Idle

Reg Data

Turn around

Idle

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