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STM32F756VG 数据表(PDF) 130 Page - STMicroelectronics |
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STM32F756VG 数据表(HTML) 130 Page - STMicroelectronics |
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130 / 228 page  Electrical characteristics STM32F756xx 130/228 DocID027589 Rev 4 tLOCK PLL lock time VCO freq = 100 MHz 75 - 200 µs VCO freq = 432 MHz 100 - 300 Jitter(3) Cycle-to-cycle jitter System clock 216 MHz RMS - 25 - ps peak to peak - ±150 - Period Jitter RMS - 15 - peak to peak - ±200 - Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples -32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples -40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples -330 - IDD(PLL)(4) PLL power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Guaranteed by characterization results. Table 43. Main PLL characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Table 44. PLLI2S characteristics Symbol Parameter Conditions Min Typ Max Unit fPLLI2S_IN PLLI2S input clock(1) -0.95(2) 12.10 MHz fPLLI2SP_OUT PLLI2S multiplier output clock for SPDIFRX - - - 216 fPLLI2SQ_OUT PLLI2S multiplier output clock for SAI - - - 216 fPLLI2SR_OUT PLLI2S multiplier output clock for I2S - - - 216 fVCO_OUT PLLI2S VCO output - 100 - 432 tLOCK PLLI2S lock time VCO freq = 100 MHz 75 - 200 µs VCO freq = 432 MHz 100 - 300 |
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