MCP8024 datasheet(23/46 Pages) MICROCHIP

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DS20005228A-page 23

MCP8024

4.4.2

LEVEL TRANSLATOR

The level translator is an interface between the com-

panion microcontrollers logic levels and the input volt-

age levels from the system. Typically, the input is

driven from the Engine Control Unit (ECU). The level

translator is a unidirectional translator. Signals on the

high-voltage input are translated to low-voltage signals

on the low-voltage outputs. The high-voltage HV_INx

inputs have a configurable 30K pullup. The pullup is

configured via a SET_CFG_0 message. Bit 6 of the

only be changed when the CE pin is active. The low-

voltage LV_OUTx outputs are open-drain outputs.

Note:

The TQFP package has two level translators.

The second level translator typically inter-

faces to an Ignition Key ON/OFF signal.

4.5

HOST COMMUNICATIONS

4.5.1

DE2 COMMUNICATIONS

A single-wire, half-duplex, 9600 baud, 8-bit bidirec-

tional communications interface is implemented using

the open-drain DE2 pin. The interface consists of eight

data bits, one Stop bit, and one Start bit. The imple-

mentation of the interface is described in the following

sections. A 2K resistor should typically be used

between the host transmit pin and the MCP8024 DE2

pin to allow the MCP8024 to drive the DE2 line when

the host TX pin is at an idle high level.

The DE2 communications is active when CE = 0 with

the constraint that the MCP8024 will not initiate any

messages. The host processor may initiate messages

regardless of the state of the CE pin. The MCP8024

will respond to host commands when the CE pin is

low.

4.5.2

PACKET FORMAT

Every internal status change will provide a communica-

tion to the microcontroller. The interface uses a stan-

dard UART baud rate of 9600 bits per second.

In the DE2 protocol, the transmitter and the receiver do

not share a clock signal. A clock signal does not ema-

nate from one transmitter to the other receiver. Due to

this reason the protocol is asynchronous. The protocol

uses only one line to communicate, so the transmit/

receive packet must be done in Half-Duplex mode. A

new transmit message is allowed only when a com-

plete packet has been transmitted.

The Host must listen to the DE2 line in order to check

for contentions. In case of contention, the host must

release the line and wait for at least three packet-length

times before initiating a new transfer.

Figure 4-2

illustrates a basic DE2 data packet.

4.5.3

PACKET TIMING

While no data is being transmitted, a logic ‘1’ must be

placed on the open-drain DE2 line by an external pull-

up resistor. A data packet is composed of one Start bit,

which is always a logic ‘0’, followed by eight data bits,

and a Stop bit. The Stop bit must always be a logic ‘1’.

It takes 10 bits to transmit a byte of data.

The device detects the Start bit by detecting the transi-

tion from logic 1 to logic 0 (note that while the data line

is idle, the logic level is high). Once the Start bit is

detected, the next data bit’s “center” can be assured to

be 24 ticks minus 2 (worst case synchronizer uncer-

tainty) later. From then on, every next data bit center is

16 clock ticks later. Figure 4-3 illustrates this point.

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