Revision 3.2

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Table4-2. CS9210Registers

Bit

Description

Index 00h

Device ID Register (RO)

Reset Value = EAh

7:0

Device Identification Register: Uniquely identifies the CS9210 device.

Index 01h

Device Revision ID Register (RO)

Reset Value = CDh

7:0

Device Revision ID Register: Uniquely identifies the revision number of a CS9210 device. This value should be verified

with a National Semiconductor representative against the actual device marking at the time of purchase.

Index 02h

Control Register (R/W)

Reset Value = 00h

7

Reset: 0 = No action, 1 = Reset entire device

6

LCD Enable: This bit cannot be enabled until all timing registers and FRM/dither memories have been programmed. The

LCD panel will not display until this bit is enabled.

0 = Disable, ENA_VDDIN input ignored and all LCD registers can be written.

1 = Enable, external ENA_VDDIN input still required to enable panel.

WARNING: When this bit is enabled, all registers except Index 02h and 03h are read only and the FRM and dither mem-

ory addresses cannot be read or written. Writing to these registers or the FRM and dither memories while this bit is

enabled will have no effect. Reading from the FRM and dither memories while this bit is enabled will return unknown data.

5

Refresh Mode: 0= 1X, 1 = 2X.

4:3

RGB Memory Map Select: Controls R/W to R, G, and B FRM and dither memory locations:

00 = Read from R memory, write to RGB

01 = Read or write to R memory

10 = Read or write to G memory

11 = Read or write to B memory

2

FRM and Dithering Mode Select: 0 = Normal, 1 = Modified.

See Section 3.8.3.1 “Modified FRM and Dithering” on page 22.)

1

16/24-Bit DSTN Select: UD/LD[11:0] formatted for: 0 = 16-bit (640x480 and 800x600), 1 = 24-bit (1024x768).

For this bit to be applicable, bit 0 must = 0. Also see Section 3.1 “Mode Selection” on page 12.

0

Pass-through: UD/LD[11:0] are formatted for: 0 = DSTN, 1 = TFT Pass-through.

A setting of 1 overrides bit 1. See Section 3.1 “Mode Selection” on page 12.

Index 03h

FRM Memory Block Select Register (R/W)

Reset Value = 00h

7:2

Reserved: Must be set to 0.

1:0

FRM Memory Block Select: There are three FRM memories; one each for R, G, and B. Each memory is 2048x1-bit to

accommodate a 32-level by 64-deep frame look-up table. R, G, and B FRM maps can be programmed individually or at

the same time. Refer to Section 3.9 “Programming the FRM and Dither Memories”.

00 = Access bits [0:511]

01 = Access bits [512:1023]

11 = Access bits [1024-1535]

11 = Access bits [1536-2047]

Index 04h-05h

Screen Width Register (R/W)

Reset Value = 0020h

15:11

Reserved: Must be set to 0.

10:0

Screen Width: 11-bit value that specifies the display width in pixels. This register must be set to the exact value of the

screen pixel width. For example, if the screen pixel width is 800, this register is set to 0320h. This value is also used to

determine how many SHFCLK pulses are required per display line on the flat panel interface.

Index 06h-07h

Screen Height Register (R/W)

Reset Value = 0004h

15:10

Reserved: Must be set to 0.

9:0

Screen Height: 10-bit value that specifies the desired display height in scan lines minus 2. This register must be set to

the exact value of the screen pixel height minus 2. For example, if the screen pixel height is 600, this register is set to 598

(256h). This value is used to determine the update of the row address on the DRAM interface.