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CS9210 数据表(PDF) 28 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 CS9210
功能描述  Geode??CS9210 Graphics Companion DSTN Controller
PDF  39 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

CS9210 数据表(HTML) 28 Page - National Semiconductor (TI)

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Revision 3.2
Register Descriptions (Continued)
Figure 4-2. Panel Power Up/Down Sequence
Table 4-3. CS9210 Registers (Power Up/Down)
Bit
Description
Index 14h
Power Up/Down Signal Delay Register (R/W)
Reset Value = 31h
7:4
Power Up Signal On Display: 4-bit value that defines the number of FP_VSYNC pulses between FP_VDDEN active and
the LCD timing signals (FLM, LP, SHFCLK, UD[11:0], and LD[11:0]) active. These bits also affect the timing of the
FP_VCONEN and DISPOFF# signals. (Refer to Figure 4-2.)
3:0
Power Down Signal Off Delay: 4-bit value that defines the number of FP_VSYNC pulses between LCD timing signals
inactive and FP_VDDEN inactive.
Index 15h
Power Up/Down LCD Enable Delay Register (R/W)
Reset Value = 23h
7:4
Power Up LCD On Delay: 4-bit value that defines the number of FP_VSYNC pulses between LCD timing signals active
and FP_VCONEN active. These bits also affect the timing of DISPOFF#. The Power Down LCD Off Delay register field
also affects the timing of FP_VDDEN. (Refer to Figure 4-2.)
3:0
Power Down LCD Off Delay: 4-bit value that defines the number of FP_VSYNC pulses between FP_VCONEN inactive
and the LCD timing signals inactive.
Index 16h
Power Up/Down Display On/Off Delay Register (R/W)
Reset Value = 12h
7:4
Power Up Display On Delay: 4-bit value that defines the number of FP_VSYNC pulses between FP_VCONEN active
and DISPOFF# active (high).
3:0
Power Down Display Off Delay: 4-bit value that defines the number of FP_VSYNC pulses between DISPOFF# inactive
(low) and FP_VCONEN inactive. These bits also affect the timing of the LCD timing signals and FP_VDDEN. (Refer to
Figure 4-2.)
Index 17h-1Fh
Reserved
00h
ENA_VDDIN
FP_VDDEN
Power Up
Signal On Delay
Power Down
Signal Off Delay
Power Up
LCD On Delay
Power Down
LCD Off Delay
FLM, LP,
SHFCLK, UD, LD
FP_VCONEN
Power Up Display
On Delay
Power Down Display
Off Delay
DISPOFF#
First FP_VSYNC after
ENA_VDDIN asserted
First FP_VSYNC after
ENA_VDDIN deasserted
Index 14h[7:4]
Index 14h[3:0]
Index 15h[7:4]
Index 15h[3:0]
Index 16h[7:4]
Index 16h[3:0]



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