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Revision 3.2

3.5

MAXIMUM FREQUENCY

The CS9210 will operate at a DOTCLK frequency of up to

65 MHz. There is no minimum frequency for the CS9210

device; however, many flat panels have signal timings that

require minimum frequencies. Refer to the flat panel dis-

play specifications as appropriate.

3.6

RESET PROCEDURES

The SCLK and DOTCLK inputs do not need to be running

when RESET# is asserted low. The assertion of RESET#

or the issue of a soft reset through the serial interface will

force the CS9210 into an internal reset state. After

RESET# is deasserted or after a soft reset is issued, the

CS9210 requires four SCLK pulses followed by ten DOT-

CLK pulses to bring it out of the internal reset state.

3.7

SERIAL INTERFACE

The serial interface is used to read and write registers and

the FRM and dithering pattern memories inside the

CS9210. One byte at a time is transferred across the

serial interface. The serial interface protocol defines an 8-

bit address for up to 256 bytes of direct addressing. The

address mapping for this 256 byte address space is

defined in Table 4-1 on page 24.

As shown in Table 3-4, the Control Register, Index 02h,

which is accessed through this serial interface, contains a

bit called LCD Enable (bit 6). This bit is turned on only

after all timing registers and FRM/Dither memories have

been programmed. The LCD panel will not power on until

this bit is enabled.

When this bit is enabled, all other registers accessed

through the serial interface become read only and cannot

be written to, and the FRM and dither memory address

ranges cannot be accessed at all. Writing to other regis-

ters or the FRM and dither memory addresses while the

LCD enable bit is enabled has no effect. Reading from the

FRM and dither memory address spaces while the LCD

enable bit is enabled returns unknown data.

Table 3-4. LCD Enable Bit

Bit

Description

Index 02h

Control Register (R/W)

Reset Value = 00h

6

LCD Enable: This bit cannot be enabled until all timing registers and FRM/dither memories have been programmed. The

LCD panel will not display until this bit is enabled.

0 = Disable, ENA_VDDIN input ignored and all LCD registers can be written.

1 = Enable, external ENA_VDDIN input still required to enable panel.

WARNING: When this bit is enabled, all registers except Index 02h and 03h are read only and the FRM and dither mem-

ory addresses cannot be read or written. Writing to these registers or the FRM and dither memories while this bit is

enabled will have no effect. Reading from the FRM and dither memories while this bit is enabled will return unknown data.