CS9210 datasheet(21/39 Pages) NSC

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Functional Description (Continued)

Figure 3-7 shows the suggested order in which 1’s should

be added to the dithering pattern as the least significant

four bits of the input intensity increase in value from 0 to

15.

Figure 3-7. 4-bit Dither Pattern Sequence

For the previous dithering pattern example where the

input intensity value was "010110", the value of the least

significant four bits is 6, which means that positions 1

through 6 in Figure 3-7 of the dithering pattern would be

setto 1,all other positionswould be setto0.Ifthe least

significant four bits have a value of 0, all sixteen positions

will be set to 0.

3.8.2.1

N-Bit Dithering Schemes

All discussions to this point have referred to a 4-bit dither-

ing scheme. A 4-bit dithering scheme is one in which the

least significant four bits of the input intensity value for

each pixel color component are truncated and these least

significant four bits are used to select a 4x4 dithering pat-

tern.

Other dithering schemes include 3-bit, 2-bit, and 1-bit dith-

ering. In the 3-bit dithering scheme, only the least signifi-

cant three bits of the input intensity value for each color

component are truncated. These three bits are then used

to select a 4x4 dithering pattern similar to the 4-bit

scheme. As the value of the least significant three bits

increases from 0 to 7, two 1’s are added to the pattern for

each increment of the 3-bit value.

The 2-bit dithering scheme selects a dithering pattern

based on the least significant two bits of the input intensity

value for each color component. As the value of these two

bits increases from 0 to 3, four 1’s are added to the pat-

tern for each increment of the 2-bit value.

The 1-bit dithering scheme uses the least significant bit of

the input intensity value to select one of two dithering pat-

terns. When the least significant bit is 0, the pattern is all

0’s. When the least significant bit is 1, the pattern is alter-

nating 0’s and 1’s.

Figure 3-8 shows the suggested order for adding 1’s to the

dithering patterns for the 3-, 2-, and 1-bit dithering

schemes.

Figure 3-8. N-Bit Dithering Pattern Schemes

X[1:0]

Y[1:0]

X[1:0]

Y[1:0]

3-Bit Scheme

X[1:0]

Y[1:0]

2-Bit Scheme

X[1:0]

Y[1:0]

1-Bit Scheme

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