Revision 3.2

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Table 4-4. CS9210 Registers (LFSR Seed, Dithering and FRM Memory Block)

Bit

Description

Index 20h-21h

Red LFSR Seed Register (R/W)

Reset Value = 00AAh

15

Reserved: Must be set to 0.

14:0

Red LFSR Seed: 15-bit value that specifies the seed value for the FRM conversion LFSR for flicker removal of the red

component of each pixel.

Index 22h-23h

Green LFSR Seed Register (R/W)

Reset Value = 0032h

15

Reserved: Must be set to 0.

14:0

Green LFSR Seed:15-bit value that specifies the seed value for the FRM conversion LFSR for flicker removal of the

green component of each pixel.

Index 24h-25h

Blue LFSR Seed Register (R/W)

Reset Value = 00h

15

Reserved: Must be set to 0.

14:0

Blue LFSR Seed: 15-bit value that specifies the seed value for the FRM conversion LFSR for flicker removal of the blue

component of each pixel.

26h-7Fh

Reserved

00h

Index 80h-9Fh

Selected Dithering Memory (R/W)

7:0

Dithering Memory Data: The dithering memory represents 16 levels of 4x4 dither, 256 bits, arranged as 32 bytes. The

Control Register, at Index 02h, selects which color component’s dither memory is being addressed; red, green or blue.

The memory organization to be used when programming the dither memory is described in Section 3.9 “Programming the

FRM and Dither Memories”.

A0h-BFh

Reserved

00h

Index C0h-FFh

Selected FRM Memory Block (R/W)

7:0

FRM Memory Data: The FRM memory represents 32 levels of 64 frame modulation data, 2048 bits, arranged as 256

bytes. The FRM memory is addressed in 512-bit (64 byte) blocks at a time. The FRM Memory Block Select register deter-

mines which of the four memory blocks is being addressed. The Control Register, at Index 02h, selects which color com-

ponent’s FRM memory is being addressed; red, green or blue. The memory organization to be used when programming

the frame modulation memory is described in Section 3.9 “Programming the FRM and Dither Memories”.