CS9210 datasheet(22/39 Pages) NSC

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Revision 3.2

Functional Description (Continued)

3.8.3

Combining FRM and Dithering

The temporal and spatial modulation techniques of FRM

and dithering are combined to reduce each input color

component intensity value down to a single bit without

sacrificing the color resolution of the original 6-bit intensity

value. Each 6-bit color component of the input pixel data

is first dithered and then the dithered value becomes the

input for FRM.

FRM and dithering can be combined in different ways. As

indicated previously, the upper five bits of the input inten-

sity value for each pixel color component selects a differ-

ent FRM sequence. This leaves only the least significant

bit of the intensity value to dither on, using the 1-bit dither-

ing scheme. By reducing the number of most significant

bits of the input intensity value that are used to select the

FRM sequence there will be more least significant bits

remaining to dither on.

For example, in a 4-bit FRM and 2-bit dithering scheme,

only the upper four bits of the input color component

intensity value would be used to select an FRM sequence

from the FRM sequence table, the remaining two bits are

then used in the 2-bit dithering scheme. Although all five

of the upper bits are used to index the FRM sequence

table, the FRM sequence table would be programmed

with duplicate FRM sequences so that the least significant

of the upper five bits has no effect on the resulting FRM

sequence.

Although 3-bit FRM/3-bit dither and 2-bit FRM/4-bit dither

modes are also supported, they are not recommended

because of the loss of spatial resolution with large dither-

ing patterns.

3.8.3.1

Modified FRM and Dithering

The CS9210 supports a mixed color generation mode

where a combination of 4-bit FRM and 2-bit dithering is

used at the extreme upper and lower values of intensity

and 5-bit FRM and 1-bit dithering is used at the middle

values of intensity. In this modified FRM and dithering

mode, when the upper four bits of the intensity value are

all 1’s or all 0’s, the 4-bit FRM and 2-bit dithering mode is

used, otherwise 5-bit FRM and 1-bit dithering is used. In

this mode, the 2-bit dithering patterns are programmed

into the CS9210 dither memories and the 1-bit dithering

patterns are implemented in hardware.

This mode enables better color perception at extreme

high and low intensities by using dithering to achieve vari-

ations in color, rather than frame rate modulation. It also

avoids the flickering effect that frame rate modulation

sometimes introduces at extreme color intensity values.

3.9

PROGRAMMING THE FRM AND DITHER

MEMORIES

The FRM sequence tables and dithering patterns for each

primary color component are stored inside fully-program-

mable memories within the CS9210. There is one FRM

memory and one dither memory for each color compo-

nent, red, green, and blue. These memories are pro-

grammed through the serial interface of the CS9210. The

serial interface writes or reads one byte at a time.

3.9.1

Addressing the FRM Memories

As previously described, the upper five bits of each color

component intensity value are used to select one of 32

different FRM sequences in the FRM sequence table.

Each FRM sequence is 64 bits long, one bit for each

frame in a 64 frame sequence. The address to one of the

FRM memories (red, green, or blue) is then a total of 11

bits, six bits from the frame count and five bits from the

intensity value. This means that for each color component

(red, green, and blue) there is one 2048x1 bit memory for

storing the FRM sequence table.

The bit address for an FRM memory is defined as the

concatenation of the 6-bit frame count and the upper five

bits of the intensity value, as shown below:

The CS9210 serial interface is a byte-addressed interface,

meaning eight bits are written to an FRM memory at a

time. The bit, located at bit address offset 0 (FRM memory

bit Address[2:0] = 0), is the first bit of the byte sent across

the serial interface. The first bit is the one marked

"Data[7]" in Figure 3-4, which describes the serial inter-

face write protocol.

The red, green, and blue FRM memories can be pro-

grammed individually, or all at once. Writing to all three

FRM memories at the same time means that the FRM

sequence table is the same for each of the three color

components. The Control Register (Index 02h) selects

which FRM memory, red, green, or blue, is selected for

read and writing.

The address for the serial interface is eight bits, allowing

256 bytes of direct addressing. Because the red, green,

and blue FRM memories are 256 bytes in size, they are

each divided into four blocks of 64 bytes. At any given

time, only one of the 64 byte blocks of FRM memory is

mapped into the serial interface address range. This is

shown in Table 4-2, Index 03h. The FRM Memory Block

Select Register is used to select which of the four blocks

of the selected FRM memory is being mapped to this

address range.

The 8-bit address presented on the serial interface is

formed by adding the base address of the FRM memory

block address space, Index C0h, to FRM memory bit

Address[8:3]. FRM memory bit Address[8:3] is the byte

offset address into the block and the block is selected by

FRM memory bit Address[10:9].

FRM Memory Bit Address[10:0]

= {FrameCount[5:0], Intensity[5:1]}

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