AD9954SLASHPCB datasheet(31/36 Pages) AD

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AD9954

Rev. 0 | Page 31 of 36

eight SCLK rising edges. The instruction byte provides the

AD9954 serial port controller with information regarding the

data transfer cycle, which is Phase 2 of the communication cycle.

The Phase 1 instruction byte defines whether the upcoming data

transfer is read or write and the serial address of the register

being accessed. [Note that the serial address of the register

being accessed is NOT the same address as the bytes to be

written. See the Example Operation section for details].

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the AD9954. The

remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the AD9954

and the system controller. The number of bytes transferred

during Phase 2 of the communication cycle is a function of the

Function Register 2, which is three bytes wide, Phase 2 requires that

three bytes be transferred. If accessing the frequency tuning word,

which is four bytes wide, Phase 2 requires that four bytes be

transferred. After transferring all data bytes per the instruction,

the communication cycle is completed.

At the completion of any communication cycle, the AD9954

serial port controller expects the next eight rising SCLK edges

to be the instruction byte of the next communication cycle. All

data input to the AD9954 is registered on the rising edge of

SCLK. All data is driven out of the AD9954 on the falling edge

of SCLK. Figure 25 through Figure 28 are useful in understand-

ing the general operation of the AD9954 serial port

INSTRUCTION CYCLE

SCLK

SDIO

DATA TRANSFER CYCLE

Figure 25. Serial Port Write Timing–Clock Stall Low

DON'T CARE

INSTRUCTION CYCLE

SCLK

SDIO

DATA TRANSFER CYCLE

DO 5 DO 4 DO 3 DO 2 DO 1

DO 0

DO 7

DO 6

SDO

Figure 26. 3-Wire Serial Port Read Timing–Clock Stall Low

INSTRUCTION CYCLE

SCLK

SDIO

DATA TRANSFER CYCLE

Figure 27. Serial Port Write Timing–Clock Stall High

DO 5 DO 4 DO 3 DO 2 DO 1 DO 0

DO 7 DO 6

INSTRUCTION CYCLE

SCLK

SDIO

DATA TRANSFER CYCLE

Figure 28. 2-Wire Serial Port Read Timing—Clock Stall High

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