AD9954SLASHPCB datasheet(14/36 Pages) AD

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AD9954

Rev. 0 | Page 14 of 36

DAC Output

The AD9954 incorporates an integrated 14-bit current output

DAC. Unlike most DACs, this output is referenced to AVDD,

not AGND.

Two complementary outputs provide a combined full-scale

output current (IOUT). Differential outputs reduce the amount of

common-mode noise that might be present at the DAC output,

offering the advantage of an increased signal-to-noise ratio. The

full-scale current is controlled by means of an external resistor

(RSET) connected between the DAC_RSET pin and the DAC

ground (AGND_DAC). The full-scale current is proportional to

the resistor value as follows

OUT

SET

The maximum full-scale output current of the combined DAC

outputs is 15 mA, but limiting the output to 10 mA provides the

best spurious-free dynamic range (SFDR) performance. The DAC

output compliance range is AVDD + 0.5 V to AVDD – 0.5 V.Volt-

ages developed beyond this range will cause excessive DAC distor-

tion and could potentially damage the DAC output circuitry.

Proper attention should be paid to the load termination to keep the

output voltage within this compliance range.

Comparator

Many applications require a square wave signal rather than a

sine wave. For example, in most clocking applications a high

slew rate helps to reduce phase noise and jitter. To support these

applications, the AD9954 includes an on-chip comparator. The

comparator has a bandwidth greater than 200 MHz and a

common-mode input range of 1.3 V to 1.8 V. By setting the

comparator power-down bit, CFR1<6>, the comparator can be

turned off to save on power consumption.

Linear Sweep Block

Linear sweep is a mode of operation whereby changes from a

start frequency (F0) to a terminal frequency (F1) are not instan-

taneous but instead are accomplished in a sweep or ramped

fashion. Frequency ramping, whether linear or nonlinear, neces-

sitates that many intermediate frequencies between F0 and F1

will be output in addition to the primary F0 and F1 frequencies.

The linear sweep block is comprised of the falling and rising

delta frequency tuning words, the falling and rising delta fre-

quency ramp rates, and the frequency accumulator. The linear

sweep enable bit CFR1 <21> enables the linear sweep block. In

addition, the linear sweep no dwell bit controls the linear sweep

block’s behavior upon reaching the terminal frequency in a

sweep. The actual method for programming a frequency sweep

is covered in the Modes of Operation section.

Serial IO Port

The AD9954 serial port is a flexible, synchronous serial communi-

cations port that allows easy interface to many industry-standard

microcontrollers and microprocessors. The serial I/O port is com-

patible with most synchronous transfer formats, including both the

Motorola 6905/11 SPI and Intel 8051 SSR protocols.

The interface allows read/write access to all registers that configure

the AD9954. MSB first or LSB first transfer formats are supported.

In addition, the AD9954’s serial interface port can be configured as

a single pin I/O (SDIO), which allows a 2-wire interface or two

unidirectional pins for in/out (SDIO/SDO), which enables a 3-wire

interface. Two optional pins, IOSYNC and CS, enable greater flexi-

bility for system design in the AD9954.

The register maps are listed in Table 7 and Table 8. The appro-

priate register map depends on the state of the linear sweep

enable bit because certain registers are remapped depending

on which mode the part is operating in

. Specifically, Registers

0x07, 0x08, 0x09, and 0x0A act as the RAM segment control

words for each of the RAM profile slices when the linear sweep

enable bit is false. When the linear sweep enable bit is true, 0x07

becomes the negative linear sweep control word and 0x08

becomes the positive linear sweep control word. The 0x09 and

0x0A registers are not used in linear sweep mode. Because the

linear sweep operation takes precedence over RAM operations,

ADI recommends that the RAM enable bit CFR1<31> be set to

zero when the linear sweep enable bit CFR1<21> is true to

conserve power. The serial address numbers associated with

each of the registers are shown in hexadecimal format. Angle

brackets <> are used to reference specific bits or ranges of bits.

For example, <3> designates Bit 3, while <7:3> designates the

range of bits from 7 down to 3, inclusive.

Table 6. Register Mapping Based on Linear Sweep Enable Bit

Linear Sweep Enable Bit

False (CFR1 <21> = 0)

RAM Segment Control Words Active

True (CFR1 <21> = 1)

Linear Sweep Control Words Active

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