AD9954SLASHPCB datasheet(33/36 Pages) AD

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AD9954

Rev. 0 | Page 33 of 36

The system must maintain synchronization with the

AD9954 or the internal control logic will not be able to

recognize further instructions. For example, if the system

sends an instruction byte that describes writing a 2-byte

additional SCLK rising edges), communication synchroni-

zation is lost. In this case, the first 16 SCLK rising edges

after the instruction cycle will properly write the first two

data bytes into the AD9954, but the next eight rising SCLK

edges are interpreted as the next instruction byte not the

final byte of the previous communication cycle. In the case

where synchronization is lost between the system and the

AD9954, the IOSYNC pin provides a means to re-establish

synchronization without re-initializing the entire chip. The

IOSYNC pin enables the user to reset the AD9954 state

machine to accept the next eight SCLK rising edges to be

coincident with the instruction phase of a new communi-

cation cycle. By applying and removing a high signal to the

IOSYNC pin, the AD9954 is set to once again begin per-

forming the communication cycle in synchronization with

the system. Any information that had been written to the

AD9954 registers during a valid communication cycle

prior to loss of synchronization will remain intact.

address specified as the beginning address. When in LSB first

mode, the first data byte will be for the least significant byte

of the memory (specified by the beginning address) with the

remaining three bytes making up the greater significant bytes of

that address. The remaining bytes come in least significant to

most significant, destined for RAM addresses generated in

ascending order until the final four bytes are written into the

memory address described by the final address. Of course, the

bit order for all bytes is least significant to most significant first

when the LSB first bit is set. When the LSB first bit is cleared

(default), the bit order for all bytes is most significant to least

significant.

The RAM uses serial address 01011(b), so the instruction byte

to write the RAM is 0×0B, in MSB first notation. As mentioned

above, the RAM addresses generated are specified by the begin-

ning and final address of the RSCW currently selected by the

Profile<1:0> pins.

Notes on serial port operation:

The AD9954 serial port configuration bits reside in Bits 8

and 9 of CFR1 (Address 0x00). The configuration changes

immediately upon writing to this register. For multibyte

transfers, writing to this register may occur during the

middle of a communication cycle. Care must be taken to

compensate for this new configuration for the remainder

of the current communication cycle.

Reading profile registers requires that the profile select pins

(Profile<1:0>) be configured to select the desired register

bank. When reading a register that resides in one of the

profiles, the register address acts as an offset to select one

of the registers among the group of registers defined by the

profile, while the profile select pins select the appropriate

Power-Down Functions of the AD9954

The AD9954 supports an externally controlled or hardware

power-down feature as well as the more common software pro-

grammable power-down bits found in previous ADI DDS products.

The software control power-down allows the DAC, comparator,

PLL, input clock circuitry, and the digital logic to be individu-

ally power down via unique control bits (CFR1<7:4>). With the

exception of CFR1<6>, these bits are not active when the exter-

nally controlled power-down pin (PWRDWNCTL) is high.

External power-down control is supported on the AD9954 via

the PWRDWNCTL input pin. When the PWRDWNCTL input

pin is high, the AD9954 will enter a power-down mode based

on the CFR1<3> bit. When the PWRDWNCTL input pin is low,

the external power-down control is inactive.

When the CFR1<3> bit is 0, and the PWRDWNCTL input pin

is high, the AD9954 is put into a fast recovery power-down

mode. In this mode, the digital logic and the DAC digital logic

are powered down. The DAC bias circuitry, comparator, PLL,

oscillator, and clock input circuitry is NOT powered down. The

comparator can be powered down by setting the comparator

power-down bit, CFR1<6> = 1.

When the CFR1<3> bit is high, and the PWRDWNCTL input

pin is high, the AD9954 is put into the full power-down mode.

In this mode, all functions are powered down. This includes the

DAC and PLL, which take a significant amount of time to

power up.

When the PWRDWNCTL input pin is high, the individual

power-down bits (CFR1<7>, <5:4>) are invalid (Don’t Care)

and unused; however, the comparator power-down bit,

CFR1<6>, will continue to control the power-down of the com-

parator.When the PWRDWNCTL input pin is low, the individual

power-down bits control the power-down modes of operation.

Note that the power-down signals are all designed such that a

Logic 1 indicates the low power mode and a Logic 0 indicates

the active or powered up mode.

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