AD9954SLASHPCB datasheet(24/36 Pages) AD

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AD9954

Rev. 0 | Page 24 of 36

completes a cycle, the RAM address generator increments to the

next address, and the timer reloads the ramp rate bits and con-

tinues counting down. This sequence continues until the RAM

address generator has incremented to an address equal to the

RAM segment final address bits of the current RSCW. Upon

reaching this terminal address, the RAM address generator

reloads the RAM segment beginning address bits and the

sequence repeats.

The sequence of circulating through the specified RAM

addresses repeats for as long as the part is programmed for this

mode. The no dwell bit is a Don’t Care in this mode.

RAM Controlled Modes of Operation Notes and Summary

Notes:

The user must ensure that the beginning address is lower

than the final address.

Changing profiles or issuing an I/O UPDATE automatically

terminates the current sweep and starts the next sweep.

Setting the RAM destination bit true such that the RAM

output drives the phase offset adder is valid. While the

above discussion describes a frequency sweep, a phase

sweep operation is also available.

The AD9954 offers five modes of RAM controlled operation

(see Table 9).

Table 9. RAM Modes of Operation

RSCW<7:5>

(Binary)

Mode

Notes

000

Direct Switch

No Sweeping, Profiles

Valid, No Dwell Invalid

001

Ramp Up

Sweeping, Profiles Valid,

No Dwell Valid

010

Bidirectional

Ramp

Sweeping, Profile <0> Is a

Direction Control Bit, No

Dwell Invalid

011

Continuous

Bidirectional

Ramp

Sweeping, Profiles Valid,

No Dwell Invalid

100

Continuous

Recirculate

Sweeping, Profiles Valid,

No Dwell Invalid

101, 110, 111

Open

Invalid Mode—Default To

Direct Switch

Internal Profile Control

The AD9954 offers a mode in which a composite frequency

sweep can be built, for which the timing control is software

programmable. The internal profile control capability disen-

gages the Profile<1:0> pins and enables the AD9954 to take

control of switching between profiles. Modes are defined that

allow continuous or single burst profile switches for three com-

binations of profile selection bits. These are listed in Table 10.

When any of the CFR1<29:27> bits are active, the

internal profile control mode is engaged. Internal profile control

is only valid when the device is operating in RAM mode. There

is no internal profile control for linear sweeping operations.

When the internal profile control mode is engaged, the RAM

segment mode control bits are Don’t Care and the device oper-

ates all profiles as if these mode control bits were programmed

for ramp-up mode. Switching between profiles occurs when the

RAM address generator has exhausted the memory contents for

the current profile.

Table 10. Internal Profile Control

CFR1<29:27>

(Binary)

Mode Description

000

Internal Control Inactive

001

Internal Control Active, Single Burst, Activate

Profile 0, Then 1, Then Stop

010

Internal Control Active, Single Burst, Activate

Profile 0, Then 1, Then 2, Then Stop

011

Internal Control Active, Single Burst, Activate

Profile 0, Then 1, Then 2, Then 3, Then Stop

100

Internal Control Active, Continuous, Activate

Profile 0, Then 1, Then Loop Starting 0

101

Internal Control Active, Continuous, Activate

Profile 0, Then 1, Then 2, Then Loop Starting 0

110

Internal Control Active, Continuous, Activate

Profile 0, Then 1, Then 2, Then 3, Then Loop

Starting 0

111

Invalid

A single burst mode is one in which the composite sweep is

executed once. For example, assume the device is programmed

for ramp-up mode and the CFR1<29:27> bits are written to

Logic 010(b). Upon receiving an I/O UPDATE, the internal

control logic signals the device to begin executing the ramp-up

mode sequence for Profile 0. Upon reaching the RAM segment

final address value for Profile 0, the device automatically

switches to Profile 1 and begins executing that ramp-up

sequence. Upon reaching the RAM segment final address value

for Profile 1, the device automatically switches to Profile 2 and

begins executing that ramp-up sequence. When the RAM seg-

ment final address value for Profile 2 is reached, the sequence is

over and the composite sweep has completed. Issuing another

I/O UPDATE restarts the burst process.

A continuous internal profile control mode is one in which the

composite sweep is continuously executed for as long as the

device is programmed into that mode. Using the example above,

except programming the CFR1<29:27> bits to Logic 101(b), the

operation would be identical until the RAM segment final

address value for Profile 2 is reached. At this point, instead of

stopping the sequence, it repeats, starting with Profile 0.

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