AD9954SLASHPCB datasheet(32/36 Pages) AD

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AD9954

Rev. 0 | Page 32 of 36

INSTRUCTION BYTE

The instruction byte contains the following information:

Table 12.

MSB

LSB

R/Wb

R/Wb—Bit 7 of the instruction byte determines whether a read

or write data transfer will occur after the instruction byte write.

Logic High indicates read operation. Logic 0 indicates a write

operation.

X, X—Bits 6 and 5 of the instruction byte are Don’t Care.

A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte

determine which register is accessed during the data transfer

portion of the communications cycle.

SERIAL INTERFACE PORT PIN DESCRIPTION

SCLK—Serial Clock. The serial clock pin is used to synchronize

data to and from the AD9954 and to run the internal state ma-

chines. SCLK maximum frequency is 25 MHz.

CSB—Chip Select Bar. CSB is active low input that allows more

than one device on the same serial communications line. The

SDO and SDIO pins will go to a high impedance state when this

input is high. If driven high during any communications cycle,

that cycle is suspended until CS is reactivated low. Chip select

can be tied low in systems that maintain control of SCLK.

SDIO — Serial Data I/O. Data is always written into the

AD9954 on this pin. However, this pin can be used as a

bidirectional data line. Bit 7 of Register Address 0x0 controls

the configuration of this pin. The default is Logic 0, which

configures the SDIO pin as bidirectional.

SDO—Serial Data Out. Data is read from this pin for protocols

that use separate lines for transmitting and receiving data. In the

case where the AD9954 operates in a single bidirectional I/O

mode, this pin does not output data and is set to a high imped-

ance state.

IOSYNC—It synchronizes the I/O port state machines without

affecting the addressable registers contents. An active high input

on the IOSYNC pin causes the current communication cycle to

abort. After IOSYNC returns low (Logic 0), another communi-

cation cycle may begin, starting with the instruction byte write.

MSB/LSB TRANSFERS

The AD9954 serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by the Control Register 0x00 <8> bit.

The default value of Control Register 0x00 <8> is low (MSB

first). When Control Register 0x00 <8> is set high, the AD9954

serial port is in LSB first format. The instruction byte must be

written in the format indicated by Control Register 0x00 <8>. If

the AD9954 is in LSB first mode, the instruction byte must be

written from least significant bit to most significant bit.

For MSB first operation, the serial port controller will generate

the most significant byte (of the specified register) address first

followed by the next lesser significant byte addresses until the

I/O operation is complete. All data written to (read from) the

AD9954 must be (will be) in MSB first order. If the LSB mode is

active, the serial port controller will generate the least signifi-

cant byte address first followed by the next greater significant

byte addresses until the I/O operation is complete. All data writ-

ten to (read from) the AD9954 must be (will be) in LSB first

order.

Example Operation

To write the amplitude scale factor register in MSB first format,

apply an instruction byte of 0x02 (serial address is 00010(b)).

From this instruction, the internal controller will generate an

internal byte address of 0x07 (see the register map) for the first

data byte written and an internal address of 0x08 for the next

byte written. Since the amplitude scale factor register is two

bytes wide, this ends the communication cycle.

To write the amplitude scale factor register in LSB first format,

apply an instruction byte of 0x40. From this instruction, the

internal controller will generate an internal byte address of 0x08

(see the register map) for the first data byte written and an in-

ternal address of 0x07for the next byte written. Since the ampli-

tude scale factor register is two bytes wide, this ends the com-

munication cycle.

RAM I/O VIA SERIAL PORT

Accessing the RAM via the serial port is identical to any other

serial I/O operation except that the number of bytes transferred

is determined by the address space between the beginning

address and the final address as specified in the current RAM

segment control word (RSCW). The final address describes the

most significant word address for all I/O transfers and the

beginning address specifies the least significant address.

RAM I/O supports MSB/LSB first operation. When in MSB first

mode, the first data byte will be for the most significant byte of

the memory address described by the final address with the

remaining three bytes making up the lesser significant bytes of

that address. The remaining bytes come in most significant to

least significant, destined for RAM addresses generated in

descending order until the final four bytes are written into the

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