AD9954SLASHPCB datasheet(18/36 Pages) AD

18 / 36 page

AD9954

Rev. 0 | Page 18 of 36

Name

(Serial

Address)

Bit Range

(MSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Bit 0

Default

Value

Profile

<7:0>

Rising Delta Frequency Tuning Word <7:0>

PS0 = 1

<15:8>

Rising Delta Frequency Tuning Word <15:8>

PS0 = 1

<23:16>

Rising Delta Frequency Tuning Word <23:16>

PS0 = 1

<31:24>

Rising Delta Frequency Tuning Word <31:24>

PS0 = 1

Positive

Linear

Sweep

Control

Word

(PLSCW)

(0x08)

<39:32>

Rising Sweep Ramp Rate Word <7:0>

PS0 = 1

Control Register Bit Descriptions

Control Function Register No.1 (CFR1)

The CFR1 is used to control the various functions, features,

and modes of the AD9954. The functionality of each bit is

detailed below.

CFR1<31>: RAM Enable Bit

CFR1<31> = 0 (default). When CFR1<31> is inactive, the RAM

is disabled for operation. Either single-tone mode of

operation or linear sweep mode of operation is enabled.

CFR1<31> = 1. If CFR1<31> is active, the RAM is

enabled for operation. Access control for normal operation is

controlled via the mode control bits of the RSCW for the cur-

rent profile.

CFR1<30>: RAM Destination Bit

CFR1<30> = 0 (default). If CFR1<31> is active, a Logic 0 on the

RAM destination bit (CFR1<30> = 0) configures the AD9954

such that the RAM output drives the phase accumulator (i.e.,

the frequency tuning word). If CFR1<31> is inactive,

CFR1<30> is a Don’t Care.

CFR1<30> = 1. If CFR1<31> is active, a Logic 1 on the RAM

destination bit (CFR1<30> = 1) configures the AD9954 such

that the RAM output drives the phase-offset adder (i.e., sets the

phase offset of the DDS core).

CFR1<29:27>: Internal Profile Control Bits

These bits cause the profile bits to be ignored when the RAM is

being used and puts the AD9954 into an automatic profile loop

sequence that allows the user to implement a frequency/phase

composite sweep that runs without external inputs. See the

Internal Profile Control section for more details.

CFR1<26>: Amplitude Ramp Rate Load Control Bit

CFR1<26> = 0 (default). The amplitude ramp rate timer is

loaded only upon timeout (timer == 1) and is not loaded due to

an I/O UPDATE input signal.

CFR1<26> = 1. The amplitude ramp rate timer is loaded upon

timeout (timer == 1) or at the time of an I/O UPDATE input signal.

CFR1<25>: Shaped On-Off Keying Enable Bit

CFR1<25> = 0 (default) Shaped on-off keying is

bypassed.

CFR1<25> = 1. Shaped on-off keying is enabled. When enabled,

CFR1<24> controls the mode of operation for this function.

CFR1<24>: Auto Shaped On-Off Keying Enable Bit (Only Valid

When CFR1<25> Is Active High)

CFR1<24> = 0 (default). When CFR1<25> is active, a Logic 0

on CFR1<24> enables the manual shaped on-off keying opera-

tion. Each amplitude sample sent to the DAC is multiplied by

the amplitude scale factor. See the Shaped On-Off Keying sec-

tion for details.

CFR1<24> = 1. When CFR1<25> is active, a Logic 1 on

CFR1<24> enables the auto shaped on-off keying operation.

Toggling the OSK pin high will cause the output scalar to ramp

up from zero scale to the amplitude scale factor at a rate deter-

mined by the amplitude ramp rate. Toggling the OSK pin low

will cause the output to ramp down from the amplitude scale

factor to zero scale at the amplitude ramp rate. See the Shaped

On-Off Keying section for details.

CFR1<23>: Automatic Synchronization Enable Bit

CFR1<23> = 0 (default). The automatic synchronization feature

of multiple AD9954s is inactive.

CFR1<23> = 1. The automatic synchronization feature of mul-

tiple AD9954s is active. The device will synchronize its internal

synchronization clock (SYNC_CLK) to align to the signal pre-

sent on the sync-in input. See the Synchronizing Multiple

AD9954s section for details.

CFR1<22>: Software Manual Synchronization of Multiple

AD9954

CFR1<22> = 0 (default). The manual synchronization feature is

inactive.

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