AD9954SLASHPCB datasheet(23/36 Pages) AD

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AD9954

Rev. 0 | Page 23 of 36

If the no dwell bit is clear when the RAM address generator

equals the final address, the generator stops incrementing as the

terminal frequency has been reached. The sweep is complete

and does not restart until an I/O UPDATE or change in profile

is detected to enable another sweep from the beginning to the

final RAM address as described above.

If the no dwell bit is set when the RAM address generator

equals the final address, after the next ramp rate timer cycle, the

phase accumulator is cleared. The phase accumulator remains

cleared until another sweep is initiated via an I/O UPDATE

input or change in profile.

Another application for ramp-up mode is nonsymmetrical FSK

modulation. With the RAM configured for two segments, using

the Profile<0> bit as the data input allows nonsymmetrical

ramped FSK.

Bidirectional Ramp Mode

Bidirectional ramp mode allows the AD9954 to offer a symmet-

rical sweep between two frequencies using the Profile<0> signal

as the control input. The AD9954 is programmed for bidirec-

tional ramp mode by writing the RAM enable bit true and the

RAM mode control bits of RSCW0 to Logic 010(b). In bidirec-

tional ramp mode, the Profile<1> input is ignored and the Pro-

file<0> input is the ramp direction indicator. In this mode, the

memory is not segmented and uses only a single beginning and

final address. The address registers that affect the control of the

RAM are located in the RSCW associated with Profile 0.

Upon entering this mode (via an I/O UPDATE or changing

Profile<0>), the RAM address generator loads the RAM seg-

ment beginning address bits of RSCW0 and the ramp rate timer

loads the RAM segment address ramp rate bits. The RAM

drives data from the beginning address, and the ramp rate timer

begins to count down to 1. While operating in this mode, tog-

gling the Profile<0> pin does not cause the device to generate

an internal I/O UPDATE. When the Profile<0> pin is acting as

the ramp direction indicator, any transfer of data from the I/O

buffers to the internal registers can only be initiated by a rising

edge on the I/O UPDATE pin.

RAM address control now is a function of the Profile<0> input.

When the Profile<0> bit is a Logic 1, the RAM address genera-

tor increments to the next address when the ramp rate timer

completes a cycle (and reloads to start the timer again). As in

the ramp-up mode, this sequence continues until the RAM

address generator has incremented to an address equal to the

final address as long as the Profile<0> input remains high. If the

Profile<0> input goes low, the RAM address generator immedi-

ately decrements and the ramp rate timer is reloaded. The RAM

address generator will continue to decrement at the ramp rate

period until the RAM address is equal to the beginning address

as long as the Profile<0> input remains low.

The sequence of ramping up and down is controlled via the

Profile<0> input signal for as long as the part is programmed

into this mode. The no dwell bit is a Don’t Care in this mode as

is all data in the RAM segment control words associated with

Profiles 1, 2, and 3. Only the information in the RAM segment

control word for Profile 0 is used to control the RAM in the

bidirectional ramp mode.

Continuous Bidirectional Ramp Mode

Continuous bidirectional ramp mode allows the AD9954 to

offer an automatic symmetrical sweep between two frequencies.

The AD9954 is programmed for continuous bidirectional ramp

mode by writing the RAM enable bit true and the RAM mode

control bits of each profile to be used to Logic 011(b).

Upon entering this mode (via an I/O UPDATE or changing

Profile<1:0>), the RAM address generator loads the RAM seg-

ment beginning address bits of the current RSCW and the ramp

rate timer loads the RAM segment address ramp rate bits. The

RAM drives data from the beginning address, and the ramp rate

timer begins to count down to 1. When the ramp rate timer

completes a cycle, the RAM address generator increments to the

next address, and the timer reloads the ramp rate bits and con-

tinues counting down. This sequence continues until the RAM

address generator has incremented to an address equal to the

RAM segment final address bits of the current RSCW. Upon

reaching this terminal address, the RAM address generator will

decrement in value at the ramp rate until it reaches the RAM

segment beginning address. Upon reaching the beginning ad-

dress, the entire sequence repeats.

The entire sequence repeats for as long as the part is pro-

grammed for this mode. The no dwell bit is a Don’t Care in this

mode. In general, this mode is identical in control to the bidi-

rectional ramp mode except the ramp up and down is automatic

(no external control via the Profile<0> input) and switching

profiles is valid. Once in this mode, the address generator ramps

from the beginning address to the final address, then back to

the beginning address at the rate programmed into the ramp

rate register. This mode enables generation of an automatic saw

tooth sweep characteristic.

Continuous Recirculate Mode

Continuous recirculate mode allows the AD9954 to offer

an automatic, continuous unidirectional sweep between two

frequencies. The AD9954 is programmed for continuous

recirculate mode by writing the RAM enable bit true and the RAM

mode control bits of each profile to be used to Logic 100(b).

Upon entering this mode (via an I/O UPDATE or changing

Profile<1:0>), the RAM address generator loads the RAM seg-

ment beginning address bits of the current RSCW and the ramp

rate timer loads the RAM segment address ramp rate bits. The

RAM drives data from the beginning address, and the ramp rate

timer begins to count down to 1. When the ramp rate timer

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