AD9954

Rev. 0 | Page 6 of 36

Parameter

Temp

Test

Level

Min

Typ

Max

Unit

Maximum Data Valid Time

FULL

IV

25

ns

Wake-Up Time4

FULL

IV

1

ms

Minimum Reset Pulse Width High

FULL

IV

5

SYSCLK Cycles5

I/O UPDATE, PS0, PS1 to SYNCCLK Setup Time DVDD_I/O = 3.3 V

FULL

I

4

ns

I/O UPDATE, PS0, PS1 to SYNCCLK Setup Time DVDD_I/O = 3.3 V

FULL

I

6

ns

I/O UPDATE, PS0, PS1 to SYNCCLK Hold Time

FULL

I

0

ns

Latency

I/O UPDATE to Frequency Change Prop Delay

25°C

IV

24

SYSCLK Cycles

I/O UPDATE to Phase Offset Change Prop Delay

25°C

IV

24

SYSCLK Cycles

I/O UPDATE to Amplitude Change Prop Delay

25°C

IV

16

SYSCLK Cycles

PS0, PS1 to RAM Driven Frequency Change Prop Delay

25°C

IV

28

SYSCLK Cycles

PS0, PS1 to RAM Driven Phase Change Prop Delay

25°C

IV

28

SYSCLK Cycles

PS0 to Linear Frequency Sweep Prop Delay

25°C

IV

28

SYSCLK Cycles

CMOS LOGIC INPUTS

Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V

25°C

I

1.25

V

Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V

25°C

I

0.6

V

Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V

25°C

I

2.2

V

Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V

25°C

I

0.8

V

Logic 1 Current

25°C

V

3

12

µA

Logic 0 Current

25°C

12

µA

Input Capacitance

25°C

2

pF

CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V

Logic 1 Voltage

25°C

I

1.35

V

Logic 0 Voltage

25°C

I

0.4

V

CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V

Logic 1 Voltage

25°C

I

2.8

V

Logic 0 Voltage

25°C

I

0.4

V

POWER CONSUMPTION (AVDD = DVDD = 1.8 V)

Single Tone Mode (Comparator Off)

25°C

I

162

171

mW

With RAM or Linear Sweep Enabled

25°C

I

175

190

mW

With Comparator Enabled

25°C

I

180

190

mW

With RAM and Comparator Enabled

25°C

I

198

220

mW

Rapid Power-Down Mode

25°C

I

150

160

mW

Full-Sleep Mode

25°C

I

20

27

mW

SYNCHRONIZATION FUNCTION6

Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V)

25°C

VI

62.5

MHz

Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V)

25°C

VI

100

MHz

SYNC_CLK Alignment Resolution7

25°C

V

±1

SYSCLK Cycles

formance of the device.

clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DAC_BP and that the recommended PLL loop filter values are used.

the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK fre-

quency is the same as the external reference clock frequency.

≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set.

edges are aligned, the synchronization function should not increase the skew between the two edges.