AD9954SLASHPCB datasheet(28/36 Pages) AD

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AD9954

Rev. 0 | Page 28 of 36

control the output amplitude by writing the scale factor value

into the amplitude scale factor (ASF) register.

The shaped on-off keying function may be bypassed (disabled)

by clearing the OSK enable bit (CFR1<25> = 0).

The modes are controlled by two bits located in the most sig-

nificant byte of the control function register (CFR). CFR1<25>

is the shaped on-off keying enable bit. When CFR1<25> is set,

the output scaling function is enabled; CFR1<25> bypasses the

function. CFR1<24> is the internal shaped on-off keying active

bit. When CFR1<24> is set, internal shaped on-off keying mode

is active; CFR1<24> cleared is external shaped on-off keying

mode active. CFR1<24> is a Don’t Care if the shaped on-off

keying enable bit (CFR1<25>) is cleared. The power up condi-

tion is shaped on-off keying disabled (CFR1<25> = 0).

Figure 22 shows the block diagram of the OSK circuitry.

AUTO Shaped On-Off Keying Mode Operation

The auto shaped on-off keying mode is active when CFR1<25>

and CFR1<24> are set. When auto shaped on-off keying mode

is enabled, a single scale factor is internally generated and

applied to the multiplier input for scaling the output of the DDS

core block (see Figure 22). The scale factor is the output of a

14-bit counter that increments/decrements at a rate determined

by the contents of the 8-bit output ramp rate register. The scale

factor increases if the OSK pin is high and decreases if the OSK

pin is low. The scale factor is an unsigned value such that all 0s

multiply the DDS core output by 0 (decimal) and 0x3FFF mul-

tiplies the DDS core output by 16383 (decimal).

For those users who use the full amplitude (14-bits) but need

fast ramp rates, the internally generated scale factor step size

is controlled via the ASF<15:14> bits. Table 11 describes the

increment/decrement step size of the internally generated scale

factor per the ASF<15:14> bits.

A special feature of this mode is that the maximum output

amplitude allowed is limited by the contents of the amplitude

scale factor register. This allows the user to ramp to a value less

than full scale.

Table 11. Auto-Scale Factor Internal Step Size

ASF<15:14> (Binary)

Increment/Decrement Size

OSK Ramp Rate Timer

The OSK ramp rate timer is a loadable down counter, which

generates the clock signal to the 14-bit counter that generates

the internal scale factor. The ramp rate timer is loaded with the

value of the ASFR every time the counter reaches 1 (decimal).

This load and countdown operation continues for as long as the

timer is enabled, unless the timer is forced to load before reach-

ing a count of 1.

If the load OSK timer bit (CFR1<26>) is set, the ramp rate timer

is loaded upon an I/O UPDATE, upon a change in profile input,

or upon reaching a value of 1. The ramp timer can be loaded

before reaching a count of 1 by three methods.

Method one is by changing the OSK input pin. When the OSK

input pin changes state, the ASFR value is loaded into the ramp

rate timer, which then proceeds to count down as normal.

The second method in which the sweep ramp rate timer can be

loaded before reaching a count of 1 is if the load OSK timer bit

(CFR1<26>) is set and an I/O UPDATE (or change in profile) is

issued.

The last method in which the sweep ramp rate timer can be

loaded before reaching a count of 1 is when going from the

inactive auto shaped on-off keying mode to the active auto

shaped on-off keying mode. That is, when the sweep enable bit

is being set.

OSK PIN

LOAD OSK TIMER

CFR1<26>

SYNC_CLK

AUTO DESK

EMABLE

CFR1<24>

TO DAC

AUTO SCALE

FACTOR GENERATOR

RAMP RATE TIMER

CLOCK

DDS CORE

OSK ENABLE

CFR<25>

AMPLITUDE SCALE

FACTOR REGISTER

(ASF)

HOLD

INC/DEC ENABLE

OUT

COS(X)

AMPLITUDE RAMP

RATE REGISTER

(ASF)

UP/DN

DATA

LOAD

Figure 22. On-Off Shaped Keying, Block Diagram

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