AD9954SLASHPCB datasheet(27/36 Pages) AD

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AD9954

Rev. 0 | Page 27 of 36

Programming the Ramp Rate Timer

The linear sweep ramp rate timer is a loadable down counter

that, when enabled, continuously counts down from the loaded

value to a count of 1. When in a rising transition, the loaded

value is the RSRRW; when in a falling transition, the value is the

FSRRW. When the ramp rate timer equals 1, the proper

RFDTW or FDFTW is loaded and the counter begins counting

down to 1 again. This load and count down operation continues

for as long as the timer is enabled, unless the timer is forced to

load before reaching a count of 1.

The ramp timer can be loaded before reaching a count of 1 by

three methods.

Method one is by changing the PS<0> input pin. When the

PS<0> input pin changes from a Logic 0 to a Logic 1, the

RSRRW value is loaded into the ramp rate timer, which then

proceeds to count down as normal. When the Profile<0> input

pin changes from a Logic 1 to a Logic 0, the FSRR value is

loaded into the ramp rate timer, which then proceeds to count

down as normal.

The second method in which the sweep ramp rate timer can be

loaded before reaching a count of 1 is if the CFR1<15> bit is set

and an I/O UPDATE is issued. If sweep is enabled and

CFR1<15> is set, the ramp rate timer loads the value deter-

mined by the Profile<0> pin every time an I/O UPDATE is

issued. If the Profile<0> pin is low (high), the ramp rate timer

loads the FSRRW (RSRRW).

The last method in which the sweep ramp rate timer can be

loaded before reaching a count of 1 is going from the inactive

linear sweep mode to the active linear sweep mode. That is

when the sweep enable bit is being set. The ramp rate loaded is a

function of the Profile<0> input pin.

Continuous and “Clear and Release” Frequency and Phase

Accumulator Clear Functions

The AD9954 allows for a programmable continuous zeroing of

the frequency sweep logic and the phase accumulator as well as

a clear and release or automatic zeroing function. Each feature is

individually controlled via Bits CFR1. CFR1<14> is the auto-

matic clear frequency accumulator bit and CFR1<13> is the

automatic clear phase accumulator bit. The continuous clear

bits are located in CFR1<11:10>, where CFR1<11> clears the

frequency accumulator and CFR1<10> clears the phase accu-

mulator.

Continuous Clear Bits

The continuous clear bits are simply static control signals that,

when active high, hold the respective accumulator at zero for

the entire time the bit is active. When the bit goes low, inactive,

the respective accumulator is allowed to operate.

Clear and Release Function

The auto clear frequency accumulator bit, when set, clears

and releases the frequency accumulator upon receiving an I/O

UPDATE signal or change in one of the profile pins. The auto

clear phase accumulator, when set, clears and releases the phase

accumulator upon receiving an I/O UPDATE or change on one

of the profile pins. The automatic clearing function is repeated

for every subsequent I/O UPDATE or change on one of the

profile pins until the appropriate auto-clear control bit is

cleared.

Note that these bits are programmed independently and do not

have to be active at the same time. For example, one accumula-

tor may be using the clear and release function while the other

is continuously cleared.

Programming AD9954 Features

Phase Offset Control

A 14-bit phase offset (θ) may be added to the output of the

phase accumulator by means of the control registers. This fea-

ture provides the user with three different methods of phase

control.

The first method is a static phase adjustment, where a fixed

phase offset is loaded into the appropriate phase offset register

and left unchanged. The result is that the output signal is offset

by a constant angle relative to the nominal signal. This allows

the user to phase align the DDS output with some external sig-

nal, if necessary.

The second method of phase control is where the user regularly

updates the phase offset register via the I/O port. By properly

modifying the phase offset as a function of time, the user can

implement a phase modulated output signal. However, both the

speed of the I/O port and the frequency of SYSCLK limit the

rate at which phase modulation can be performed.

The third method of phase control involves the RAM and the

profile input pins. The AD9954 can be configured such that the

RAM drives the phase adjust circuitry. The user can control the

phase offset via the RAM in an identical manner allowed for

frequency sweeping. See the RAM Controlled Modes of Opera-

tion and the Linear Sweep Mode sections for details.

Shaped On-Off Keying

The shaped on-off keying function of the AD9954 allows the

user to control the ramp-up and ramp-down time of an on-off

emission from the DAC. This function is used in burst trans-

missions of digital data to reduce the adverse spectral impact of

short, abrupt bursts of data.

Auto and manual shaped on-off keying modes are supported.

The auto mode generates a linear scale factor at a rate deter-

mined by the amplitude ramp rate (ARR) register controlled by

an external pin (OSK). Manual mode allows the user to directly

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