AD9954SLASHPCB datasheet(20/36 Pages) AD

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AD9954

Rev. 0 | Page 20 of 36

CFR1<3>: External Power-Down Mode

CFR1<3> = 0 (default). The external power-down mode

selected is the rapid recovery power-down mode. In this mode,

when the PWRDWNCTL input pin is high, the digital logic and

the DAC digital logic are powered down. The DAC bias cir-

cuitry, comparator, PLL, oscillator, and clock input circuitry are

not powered down.

CFR1<3> = 1. The external power-down mode selected is the

full power-down mode. In this mode, when the PWRDWNCTL

input pin is high, all functions are powered down. This includes

the DAC and PLL, which take a significant amount of time to

power up.

CFR1<2>: Linear Sweep No Dwell Bit

CFR1<2> = 0 (default). The linear sweep no dwell function is

inactive.

CFR1<2> = 1. The linear sweep no dwell function is active. If

CFR1<21>, the linear sweep enable bit, is active and CFR1<2> is

active, the linear sweep no dwell function is activated. See the

Linear Sweep Mode section for details. If CFR1<21> is clear,

this bit is a Don’t Care.

CFR1<1>: SYNC_CLK Disable Bit

CFR1<1> = 0 (default). The SYNC_CLK pin is active.

CFR1<1> = 1. The SYNC_CLK pin assumes a static Logic 0

state to keep noise generated by the digital circuitry at a mini-

mum. However, the synchronization circuitry remains active

(internally) to maintain normal device timing.

CFR1<0>: Not Used, Leave at 0

Control Function Register No.2 (CFR2)

The CFR2 is used to control the various functions, features, and

modes of the AD9954, primarily related to the analog sections

of the chip.

CFR2<15:12>: Not Used

CFR2<11>: High Speed Sync Enable Bit

CFR2<11> = 0 (default). The high speed sync enhancement is

off.

CFR2<11> = 1. The high speed sync enhancement is on. This

bit should be set when attempting to use the auto-

synchronization feature for SYNC_CLK inputs beyond 50 MHz,

(200 MSPS SYSCLK). See the Synchronizing Multiple AD9954s

section for details.

CFR2<10>: Hardware Manual Sync Enable Bit

CFR2<10> = 0 (default). The hardware manual sync function is

off.

CFR2<10> = 1. The hardware manual sync function is enabled.

While this bit is set, a rising edge on the SYNC_IN pin will

cause the device to advance the SYNC_CLK rising edge by one

REFCLK cycle. Unlike the software manual sync enable bit, this

bit does not self-clear. Once the hardware manual sync mode is

enabled, it will stay enabled until this bit is cleared. See the

Synchronizing Multiple AD9954s section for details.

CFR2<9>: CRYSTAL OUT Enable Bit

CFR2<9> = 0 (default). The CRYSTAL OUT pin is inactive.

CFR2<9> = 1. The CRYSTAL OUT pin is active. When active,

the crystal oscillator circuitry output drives the CRYSTAL OUT

pin, which can be connected to other devices to produce a refer-

ence frequency. The oscillator will respond to crystals in the

range of 20 MHz to 30 MHz.

CFR2<8>: Not Used

CFR2<7:3>: Reference Clock Multiplier Control Bits

This 5-bit word controls the multiplier value out of the clock-

multiplier (PLL) block. Valid values are decimal 4 to 20 (0×04 to

0×14). Values entered outside this range will bypass the clock

multiplier. See the Phase-Locked Loop (PLL) section for details.

CFR2<2>: VCO Range Control Bit

This bit is used to control the range setting on the VCO.

When CFR2<2> == 0 (default), the VCO operates in a range of

100 MHz to 250 MHz. When CFR2<2> == 1, the VCO operates

in a range of 250 MHz to 400 MHz.

CFR2<1:0>: Charge Pump Current Control Bits

These bits are used to control the current setting on the charge

pump. The default setting, CFR2<1:0>, sets the charge pump

current to the default value of 75 µA. For each bit added (01, 10,

11) 25 µA of current is added to the charge pump current:

100 µA, 125 µA, and 150 µA.

Other Register Descriptions

Amplitude Scale Factor (ASF)

The ASF register stores the 2-bit auto ramp rate speed value and

the 14-bit amplitude scale factor used in the output shaped key-

ing (OSK) operation. In auto OSK operation, ASF <15:14> tells

the OSK block how many amplitude steps to take for each

increment or decrement. ASF<13:0> sets the maximum value

achievable by the OSK internal multiplier. In manual OSK

mode, ASF<15:14> has no effect. ASF <13:0> provide the output

scale factor directly. If the OSK enable bit is cleared, CFR1<25>

= 0, this register has no effect on device operation.

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