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AD9954

Rev. 0 | Page 25 of 36

Linear Sweep Mode

The AD9954 is placed in linear sweep mode by setting the lin-

ear sweep enable bit CR1<21>. When in linear sweep mode, the

AD9954 output frequency will ramp up from a starting fre-

quency, programmed by FTW0 to a finishing frequency FTW1,

or down from FTW1 to FTW0. The delta frequency tuning

words and the ramp rate word determine the rate at which this

ramping takes place. The linear sweep no-dwell bit CFR1<2>

controls the behavior of the device upon reaching the terminal

frequency. The 32-bit rising delta frequency tuning word

(RDFTW) increments the frequency accumulator when ramp-

ing up from FTW0 to FTW1. The 8-bit rising sweep ramp rate

word (RSRRW) controls the rate at which the frequency accu-

mulator is incremented. The 32-bit falling delta frequency tun-

ing word (FDFTW) decrements the accumulator when ramping

down from FTW1 to FTW0. The 8-bit falling sweep ramp rate

word (FSRRW) determines the rate at which the accumulator is

decremented.

The PS<0> pin controls the direction of the sweep, rising to

FTW1 or falling to FTW0. Upon reaching the destination fre-

quency, the AD9954 linear sweep function will either hold at the

destination frequency until the state on the PS<0> pin is

changed or immediately return to the initial frequency, FTW0,

depending on the state of the linear sweep no-dwell bit

CFR1<02>. While operating in linear sweep mode, toggling the

Profile<0> pin does not cause the device to generate an internal

I/O UPDATE. When the PS<0> pin is acting as the sweep direc-

tion indicator, any transfer of data from the I/O buffers to the

internal registers can only be initiated by a rising edge on the

I/O UPDATE pin.

The linear sweep function of the AD9954 requires the lowest

frequency to be loaded into the FTW0 register and the highest

frequency into the FTW1 register. For piece-wise, nonlinear

frequency transitions, it is necessary to reprogram the registers

while the frequency transition is in progress to affect the desired

response. Figure 20 demonstrates a typical frequency ramping

operation. After a reset, the device will initially be in single tone

mode. The programming steps to operate in linear sweep mode

are

Profile inputs at 00.

Set the linear sweep enable bit (CFR1<21> = 1) and

set or clear the linear sweep no-dwell bit (CFR1<2> =

{0,1}) as desired.

Program the rising and falling delta frequency tuning

words and ramp rate values.

Program the lower and higher output frequencies into

the FTW0 and FTW1 registers, respectively.

Apply an I/O UPDATE to move this data into the reg-

isters (the output frequency will be FTW0).

Change the PS<0> input as desired to sweep between

the lower to higher frequency and back.

Figure 20 shows that the device initially powers up in single

tone mode. The profile inputs are low, which places the FTW0

input to the phase accumulator. The user then configures the

device as desired by writing the rising and falling delta

frequency tuning words and ramp rates, as well as the linear

sweep enable bit, via the serial port (Point A in Figure 20). In this

example, the linear sweep no-dwell bit is cleared (CFR1<2> = 0).

General Operation of Linear Sweep Capability

In linear sweep mode, the PS<1> pin must be tied to Logic 0.

With linear sweep mode active, when the PS<0> pin transitions

from low to high, the RDFTW is applied to the input of the

frequency accumulator and the RSRR register is loaded into the

sweep rate timer. The sweep rate timer counts down from an

initial value to one, at which point the frequency accumulator is

allowed to accumulate the input. This accumulation of the

RDFTW at the rate given by the ramp rate (RSRR) continues

until the output of the frequency adder is equal to the FTW1

the AD9954 to output the frequency given by the FTW1. The

output remains at FTW1 for as long as the PS<0> pin remains

at Logic 1.

When the PS<0> pin transitions from high to low, the

negated FDFTW is applied to the input of the frequency accu-

mulator and the FSRR register is loaded into the sweep rate

timer. Each time the timer counts down to one, the frequency

accumulator is allowed to accumulate the input. This accumula-

tion of the negated FDFTW at the rate given by the ramp rate

(FSRR) continues until the output of the frequency adder is

equal to the FTW0 register value. At this time the accumulation

is stopped, causing the AD9954 to output the frequency given

by the FTW0. The output remains at FTW0 for as long as the

PS<0> pin remains at Logic 0.

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