TAS3208IPZP datasheet(32/79 Pages) TI1

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I2C EEPROM Memory Map

Block Header 1

Block Header 2

Block Header N

…

Data Block N

Data Block 1

Data Block 2

TAS3208

SLES201E

– JANUARY 2007 – REVISED MARCH 2011

www.ti.com

Figure 23. EEPROM Address Map

The TAS3208 will sequentially read EEPROM memory and load its internal memory unless it does not find a

valid memory header block, is not able to read the next memory location because the end of memory was

reached, detects a checksum error, or reads a end-of-program header block. When it encounters a valid header

or read error, the TAS3208 will attempt to read the header or memory location three times before it determines

that it has an error. If the TAS3208 encounters a checksum error, it will attempt to reread the entire block of

memory two more times before it determines that it has an error.

NOTE

Once the microprogram memory has been loaded, it can not be reloaded until the

TAS3208 has been reset.

If an error is encountered, the TAS3208 terminates its memory load operation, loads the default configuration for

both the M8051 MCU and DSP from the embedded ROM, and disables further master I2C bus operations.

If an end-of-program data block is read, the TAS3208 has completed the initial program load.

The I2C master mode utilizes the starting and ending I2C checksums to verify a proper EEPROM download. The

first 16-bit data word received from the EEPROM is the I2C checksum at subaddress 0x00. It is stored and

compared against the 16-bit data word received for last subaddress, the ending I2C checksum, and the

checksum that is computed during the download. These three values must be equal. If the read and computed

values do not match, the TAS3208 sets the memory read error bits in the Status register and repeats the

download from the EEPROM two more times. If the comparison check again fails the third time, the TAS3208

sets the microprogram to the default value.

NOTE

When acting as an I2C master, the data rate transfer is fixed at 375 kHz.

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